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1.1 ! root 1: /* ! 2: This routine locate the error at ! 3: the board level. ! 4: */ ! 5: #include "definitions" ! 6: extern struct OPTIONS OPTIONS; ! 7: ! 8: extern long maxmem,endprog,scb; ! 9: extern long eccloc(), cycle,test_no,errcnt; ! 10: extern long loop_flg,hlt_flg,prt_flg; ! 11: ! 12: extern struct tmp_mcbr{ ! 13: unsigned :2; ! 14: unsigned syndrome :7; ! 15: unsigned chk_bits :7; ! 16: unsigned :14; ! 17: unsigned versabus_type :2; ! 18: } tmp_mcbr; ! 19: ! 20: extern struct tmp_mear{ ! 21: unsigned mear :16; ! 22: unsigned :10; ! 23: unsigned ber :1; ! 24: unsigned erm :1; ! 25: unsigned axe :1; ! 26: unsigned err_code :3; ! 27: } tmp_mear; ! 28: ! 29: struct mcbr{ ! 30: unsigned :18; ! 31: unsigned synd_bits :7; ! 32: unsigned check_bits :7; ! 33: }; ! 34: ! 35: struct mer{ ! 36: unsigned :16; ! 37: unsigned :10; ! 38: unsigned ber :1; ! 39: unsigned erm :1; ! 40: unsigned axe :1; ! 41: unsigned err_code :3; ! 42: }; ! 43: ! 44: struct mcr{ ! 45: unsigned :16; ! 46: unsigned err_count : 8; ! 47: unsigned clr_error : 1; ! 48: unsigned clr_count : 1; ! 49: unsigned init : 1; ! 50: unsigned : 1; ! 51: unsigned diag_read : 1; ! 52: unsigned diag_writ : 1; ! 53: unsigned correction : 1; /* Enable Error Correction */ ! 54: unsigned detection : 1; /* Enable Error Detection */ ! 55: }; ! 56: ! 57: long *CPCR = (long *)0xffffb028; /* Ptr to CP Control register */ ! 58: ! 59: ! 60: locate(addr,exp,act) ! 61: long addr,exp,act; ! 62: { ! 63: long intl, board,b1, bank; ! 64: register struct mcr *MCR = (struct mcr *)0xffffb000; ! 65: register struct mer *MER = (struct mer *)0xffffb020; ! 66: register struct mcbr *MCBR = (struct mcbr *)0xffffb008; ! 67: ! 68: if(OPTIONS.fourmb) { ! 69: if (!(loc4mb(addr,&board,&bank,&intl))) ! 70: return(0); } ! 71: else { ! 72: if (!(locboard(addr,&board,&bank,&intl))) ! 73: return(0); } ! 74: intl = *CPCR & 3; /* Read Memory Interleave status */ ! 75: if (intl) { ! 76: if (intl==1) intl=2; ! 77: else intl = 4; ! 78: } ! 79: writes("\n"); writed(intl);writes(" ways interleave."); ! 80: writes("\nBoard # "); writed(board); ! 81: writes(", Bank # "); writed(bank,1); ! 82: writes("\nIC number(s) : "); ! 83: locic(bank,exp,act); ! 84: } ! 85: ! 86: char *names[4] = { ! 87: " U7"," U5"," U3"," U1" ! 88: }; ! 89: ! 90: locic(bk,exp,act) ! 91: long bk, exp, act; ! 92: { register long ix, bad, bit, b2; ! 93: char *this, str[4]; ! 94: ! 95: for(ix=0;ix<3;ix++) str[ix] = names[bk][ix]; ! 96: str[3] = '\0'; ! 97: this = str; ! 98: bad = exp ^ act; /* Exclusive OR */ ! 99: bit = 1; ! 100: writes("\n"); ! 101: for(ix=0;ix<32; ix++, bit <<= 1) { ! 102: if (ix == 16) this[2]++; /* Second row */ ! 103: if (bad & bit) { ! 104: /* Bit in error */ ! 105: b2 = ix; ! 106: if (ix > 15) b2 = ix-16; ! 107: writes(this); ! 108: b2 += 2; ! 109: if (b2 >= 10) { writes("1"); ! 110: b2 -= 10; ! 111: } ! 112: else writes("0"); ! 113: pt_hex(b2,1); ! 114: } ! 115: } ! 116: writes("\n"); ! 117: } ! 118: /* ! 119: locate board and bank for 1 mbyte memory array ! 120: */ ! 121: locboard(addr,board,bank,intl) ! 122: long addr; ! 123: long *board, *bank,*intl; ! 124: { ! 125: register long inl, b1; ! 126: writes("\n1 mb"); ! 127: inl = *CPCR & 3; /* Read Memory Interleave status */ ! 128: *intl = inl; ! 129: if (inl==2) { ! 130: writes("\nInvalid memory interleave status : "); ! 131: writeh(inl); ! 132: return(0); } ! 133: if (!inl) { ! 134: /* Non_interleave */ ! 135: *board = (addr & 0x3ff00000) >> 20; ! 136: *bank = (addr & 0xc0000) >> 18; ! 137: } ! 138: else { ! 139: if (inl==1) { ! 140: /* 2 ways interleave */ ! 141: *board = (addr & 0x3fd00000) >> 20; ! 142: b1 = (addr & 0x4) >> 2; ! 143: *board |= b1; ! 144: *bank = (addr & 0x180000) >> 19; ! 145: *intl = 2; ! 146: } ! 147: else { ! 148: /* 4 ways interleave */ ! 149: *board = (addr & 0x3fc00000) >> 20; ! 150: b1 = (addr & 0xc) >> 2; ! 151: *board |= b1; ! 152: *bank = (addr & 0x300000) >> 20; ! 153: *intl = 4; ! 154: } ! 155: } ! 156: return(1); ! 157: } ! 158: /* ! 159: locate board and bank for 4 mbyte memory array ! 160: */ ! 161: loc4mb(addr,board,bank,intl) ! 162: long addr; ! 163: long *board, *bank,*intl; ! 164: { ! 165: register long inl, b1; ! 166: writes("\n4 mb"); ! 167: ! 168: inl = *CPCR & 3; /* Read Memory Interleave status */ ! 169: *intl = inl; ! 170: if (inl==2) { ! 171: writes("\nInvalid memory interleave status : "); ! 172: writeh(inl); ! 173: return(0); } ! 174: if (!inl) { ! 175: /* Non_interleave */ ! 176: *board = (addr & 0x3fc00000) >> 22; ! 177: *bank = (addr & 0x300000) >> 20; ! 178: } ! 179: else { ! 180: if (inl==1) { ! 181: /* 2 ways interleave */ ! 182: *board = (addr & 0x3f800000) >> 22; ! 183: b1 = (addr & 0x4) >> 2; ! 184: *board |= b1; ! 185: *bank = (addr & 0x600000) >> 21; ! 186: *intl = 2; ! 187: } ! 188: else { ! 189: /* 4 ways interleave */ ! 190: *board = (addr & 0x3f000000) >> 22; ! 191: b1 = (addr & 0xc) >> 2; ! 192: *board |= b1; ! 193: *bank = (addr & 0xc00000) >> 22; ! 194: *intl = 4; ! 195: } ! 196: } ! 197: return(1); ! 198: }
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