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Annotation of cci/d/mem/tahoe.def, revision 1.1

1.1     ! root        1: #      Processor storage(8000) physical memory
        !             2: #      This section defines those names to be used when refering to
        !             3: #      processor storage.  The use of many of these locations are defined
        !             4: #      in the architecture manual.
        !             5: #      These values always appear in the literal field.
        !             6: #
        !             7:        .set    PCBB,0x400              ;process control block base
        !             8:        .set    INTSP,0x404             ;Interrupt stack pointer
        !             9:        .set    SIRR,0x408              ;Software interrupt request
        !            10:        .set    SSR,0x40C               ;Software interrupt summary
        !            11:        .set    HSR,0x410               ;Hardware interrupt summary
        !            12:        .set    SCBB,0x414              ;Pointer to system control block base
        !            13:        .set    TBCR,0x418              ;Current value of hardware TBCR
        !            14:        .set    CPMDCB,0x420            ;pointer to CP master DCB
        !            15:        .set    CPCTL,0x424             ;CPU control word
        !            16:        .set    CPREQ,0x428             ;CPU request
        !            17:        .set    CPRUN,0x42C             ;CPU run status (8 = step mode)
        !            18:        .set    CPRSW,0x430             ;CP interrupt request word
        !            19:        .set    PSL,0x434               ;Software Process Status Longword
        !            20:        .set    TVAPR,0x5E8             ;saved vapr register
        !            21:        .set    TRA,0x5EC               ;
        !            22:        .set    TLSP,0x5F0              ;
        !            23:        .set    TIAR,0x5F4              ;
        !            24:        .set    TLIA,0x5F8              ;
        !            25:        .set    TQ,0x5FC                ;
        !            26:        .set    TR0,0x600               ;decellerated processor registers
        !            27:        .set    TR1,0x604               ;decellerated processor registers
        !            28:        .set    TR2,0x608               ;decellerated processor registers
        !            29:        .set    TR3,0x60C               ;decellerated processor registers
        !            30:        .set    TR4,0x610               ;decellerated processor registers
        !            31:        .set    TR5,0x614               ;decellerated processor registers
        !            32:        .set    TR6,0x618               ;decellerated processor registers
        !            33:        .set    TR7,0x61C               ;decellerated processor registers
        !            34:        .set    TR8,0x620               ;decellerated processor registers
        !            35:        .set    TR9,0x624               ;decellerated processor registers
        !            36:        .set    TR10,0x628              ;decellerated processor registers
        !            37:        .set    TR11,0x62C              ;decellerated processor registers
        !            38:        .set    TR12,0x630              ;decellerated processor registers
        !            39:        .set    TR13,0x634              ;decellerated processor registers
        !            40:        .set    TR14,0x638              ;decellerated processor registers
        !            41:        .set    TR15,0x63C              ;decellerated processor registers
        !            42:        .set    TPC,0x640               ;decellerated program counter
        !            43:        .set    TPSL,0x644              ;decellerated process status longword
        !            44:        .set    TSP,0x648               ;decellerated stack pointer
        !            45:        .set    TKSP,0x64C              ;decellerated kernel stack pointer
        !            46:        .set    TUSP,0x650              ;decellerated user stack pointer
        !            47:        .set    TCCK,0x654              ;decellerated Code cache key
        !            48:        .set    TDCK,0x658              ;decellerated data cache key
        !            49:        .set    TTBK,0x65C              ;decellerated translation buffer key
        !            50:        .set    TSBR,0x660              ;decellerated System Base Register
        !            51:        .set    TSLR,0x664              ;decellerated System length register
        !            52:        .set    TP0BR,0x668             ;decellerated P0 base register
        !            53:        .set    TP0LR,0x66C             ;decellerated P0 length register
        !            54:        .set    TP1BR,0x670             ;decellerated P1 base register
        !            55:        .set    TP1LR,0x674             ;decellerated P1 length register
        !            56:        .set    TP2BR,0x678             ;decellerated P2 base register
        !            57:        .set    TP2LR,0x67C             ;decellerated P1 length register
        !            58:        .set    TIPL,0x680              ;decellerated Interrupt priority level
        !            59:        .set    TMME,0x684              ;decellerated Memory management enable
        !            60:        .set    TTBIA,0x68C             ;decellerated translation buffer invalid
        !            61:        .set    TTBIS,0x68C             ;decellerated transl buffer invalid single
        !            62:        .set    TPCBB,0x690             ;decellerated Process control block base
        !            63:        .set    TISP,0x694              ;decellerated Interrupt stack pointer
        !            64:        .set    TSIRR,0x698             ;decellerated Software interrupt request
        !            65:        .set    TSISR,0x69C             ;decellerated Software interrupt summary
        !            66:        .set    TSCBB,0x6A0             ;decellerated System control block base
        !            67:        .set    TP1CC,0x6A4             ;decellerated 
        !            68:        .set    TPACC,0x6A8             ;decellerated
        !            69:        .set    TP1DC,0x6AC             ;decellerated
        !            70:        .set    TPADC,0x6B0             ;decellerated
        !            71:        .set    TCPMDCB,0x6B4           ;decellerated address of master DCB
        !            72:        .set    PROBFLG,0x6B8           ;decellerated
        !            73:        .set    INEXCFLG,0x6BC          ;decellerated
        !            74:        .set    PCTYPFLG,0x6C0          ;
        !            75:        .set    NOOFPARS,0x6C4          ;
        !            76:        .set    STKPAR1,0x6C8           ;
        !            77:        .set    STKPAR2,0x6CC           ;
        !            78:        .set    JMPVEC,0x6D0            ;
        !            79:        .set    PSEND,0x7FC             ;

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