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Power 6/32 Unix version 1.2b

#	Processor storage(8000) physical memory
#	This section defines those names to be used when refering to
#	processor storage.  The use of many of these locations are defined
#	in the architecture manual.
#	These values always appear in the literal field.
#
	.set	PCBB,0x400		;process control block base
	.set	INTSP,0x404		;Interrupt stack pointer
	.set	SIRR,0x408		;Software interrupt request
	.set	SSR,0x40C		;Software interrupt summary
	.set	HSR,0x410		;Hardware interrupt summary
	.set	SCBB,0x414		;Pointer to system control block base
	.set	TBCR,0x418		;Current value of hardware TBCR
	.set	CPMDCB,0x420		;pointer to CP master DCB
	.set	CPCTL,0x424		;CPU control word
	.set	CPREQ,0x428		;CPU request
	.set	CPRUN,0x42C		;CPU run status (8 = step mode)
	.set	CPRSW,0x430		;CP interrupt request word
	.set	PSL,0x434		;Software Process Status Longword
	.set	TVAPR,0x5E8		;saved vapr register
	.set	TRA,0x5EC		;
	.set	TLSP,0x5F0		;
	.set	TIAR,0x5F4		;
	.set	TLIA,0x5F8		;
	.set	TQ,0x5FC		;
	.set	TR0,0x600		;decellerated processor registers
	.set	TR1,0x604		;decellerated processor registers
	.set	TR2,0x608		;decellerated processor registers
	.set	TR3,0x60C		;decellerated processor registers
	.set	TR4,0x610		;decellerated processor registers
	.set	TR5,0x614		;decellerated processor registers
	.set	TR6,0x618		;decellerated processor registers
	.set	TR7,0x61C		;decellerated processor registers
	.set	TR8,0x620		;decellerated processor registers
	.set	TR9,0x624		;decellerated processor registers
	.set	TR10,0x628		;decellerated processor registers
	.set	TR11,0x62C		;decellerated processor registers
	.set	TR12,0x630		;decellerated processor registers
	.set	TR13,0x634		;decellerated processor registers
	.set	TR14,0x638		;decellerated processor registers
	.set	TR15,0x63C		;decellerated processor registers
	.set	TPC,0x640		;decellerated program counter
	.set	TPSL,0x644		;decellerated process status longword
	.set	TSP,0x648		;decellerated stack pointer
	.set	TKSP,0x64C		;decellerated kernel stack pointer
	.set	TUSP,0x650		;decellerated user stack pointer
	.set	TCCK,0x654		;decellerated Code cache key
	.set	TDCK,0x658		;decellerated data cache key
	.set	TTBK,0x65C		;decellerated translation buffer key
	.set	TSBR,0x660		;decellerated System Base Register
	.set	TSLR,0x664		;decellerated System length register
	.set	TP0BR,0x668		;decellerated P0 base register
	.set	TP0LR,0x66C		;decellerated P0 length register
	.set	TP1BR,0x670		;decellerated P1 base register
	.set	TP1LR,0x674		;decellerated P1 length register
	.set	TP2BR,0x678		;decellerated P2 base register
	.set	TP2LR,0x67C		;decellerated P1 length register
	.set	TIPL,0x680		;decellerated Interrupt priority level
	.set	TMME,0x684		;decellerated Memory management enable
	.set	TTBIA,0x68C		;decellerated translation buffer invalid
	.set	TTBIS,0x68C		;decellerated transl buffer invalid single
	.set	TPCBB,0x690		;decellerated Process control block base
	.set	TISP,0x694		;decellerated Interrupt stack pointer
	.set	TSIRR,0x698		;decellerated Software interrupt request
	.set	TSISR,0x69C		;decellerated Software interrupt summary
	.set	TSCBB,0x6A0		;decellerated System control block base
	.set	TP1CC,0x6A4		;decellerated 
	.set	TPACC,0x6A8		;decellerated
	.set	TP1DC,0x6AC		;decellerated
	.set	TPADC,0x6B0		;decellerated
	.set	TCPMDCB,0x6B4		;decellerated address of master DCB
	.set	PROBFLG,0x6B8		;decellerated
	.set	INEXCFLG,0x6BC		;decellerated
	.set	PCTYPFLG,0x6C0		;
	.set	NOOFPARS,0x6C4		;
	.set	STKPAR1,0x6C8		;
	.set	STKPAR2,0x6CC		;
	.set	JMPVEC,0x6D0		;
	.set	PSEND,0x7FC		;

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