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1.1 root 1: #include "definitions"
2: #define BEVEC 128 /* offset in scb block for Bus error*/
3: #define ecczero 0x00000028
4: #define eccone 0x0000012d
5: #define MEMUNIT 64 * 1024
6: #include "test4.h"
7:
8: extern struct OPTIONS OPTIONS;
9: extern long maxmem,endprog,scb;
10: extern long eccloc(), cycle,test_no,errcnt;
11: extern long loop_flg,hlt_flg,prt_flg;
12: extern long ber1, ber2;
13: extern long exp_ecc[];
14: long abmax;
15: subtest4()
16: {
17: register long *mcr = (long *)0xffffb000;
18: register long *mcbr = (long *)0xffffb008;
19: register long delay, *addr, bit, ckbits, dpat;
20: long oldstatus, data, code, wcnt, cnt, actual, eccloc();
21: char *msg;
22:
23: if (OPTIONS.header)
24: writes("\n** Subtest4 : ECC single bit error correction.");
25: oldstatus = *mcr; /* save old status */
26: dpat = 0;
27: ckbits = 0xc; /* Check bits for data 0 */
28: addr = (long *)abmax - 102400; /* Only check the last 100k */
29: for(wcnt=0;addr <= (long *)abmax;addr++, wcnt++)
30: {
31: again:
32: /* Write data and known good check bits pattern */
33: data = dpat; /* Test data pattern */
34: *mcbr = ckbits; /* Check bits of data 0 */
35: *mcr = 0xc4; /* Turn ON diag_write */
36: delay = *mcr;
37: *addr = data; /* Write Data with check */
38: /* bits taken from MCBR */
39: *mcr = 0; /* Turn OFF Diag_write */
40: delay = *mcr;
41: code = eccloc(addr); /* Read back data */
42: if ((code == -1) && prt_flg) { /* Got an unexpected DCE */
43: *mcr = 0xc0; /* Turn OFF ECC, clear err. */
44: writes("\nUnexpected DCE.<Diag_wr failed>");
45: writes("\nAddress : "); writeh(addr);
46: writes("\nLword count : "); writed(wcnt);
47: wr_mibreg();
48: if (loop_flg) goto again;
49: else if (hlt_flg) Halt();
50: else continue;
51: }
52: if ((code == -2) && prt_flg) {
53: *mcr = 0; /* Turn OFF ECC logic */
54: writes("\nUnexpected Buser.");
55: wr_mibreg();
56: if (loop_flg) goto again;
57: else if (hlt_flg) Halt();
58: else continue;
59: }
60: actual = *addr; /* Read data back to check */
61: if ((actual != data)&& prt_flg) {
62: writes("\nDiag_wr failed. Wrong data read back.");
63: writes("\nExpected "); writeh(data);
64: writes(", Actual "); writeh(actual);
65: if (loop_flg) goto again;
66: else if (hlt_flg) Halt();
67: else continue;
68: }
69: for(bit=1,cnt=0;cnt<32; bit <<= 1, cnt++) {
70: repeat:
71: /* Write data and known good check bits pattern */
72: data = dpat; /* Test data pattern */
73: data |= bit; /* Change 1 bit in data pattern */
74: *mcbr = ckbits; /* Check bits of data 0 */
75: *mcr = 4; /* Turn ON diag_write */
76: delay = *mcr;
77: *addr = data; /* Write Bad data back */
78: *mcr = 0; /* Turn OFF Diag_write */
79: delay = *mcr;
80: code = ecccor(addr,&actual); /* Read back data */
81: if ((code == -1) && prt_flg) {
82: /* Didnot correct bad data */
83: writes("\nGot DCE with single bit error while correction is enable..");
84: writes("\n\tData written : ");
85: writeh(data);
86: writes("\n\tCheck bits written in MCBR : ");
87: writeh(ckbits);
88: writes("\n\tAddress : "); writeh(addr);
89: wr_mibreg();
90: if (loop_flg) goto repeat;
91: else if (hlt_flg) Halt();
92: else continue;
93: }
94: if ((code == -2) && prt_flg) {
95: writes("\nUnexpected Buser");
96: wr_mibreg();
97: if (loop_flg) goto repeat;
98: else if (hlt_flg) Halt();
99: else continue;
100: }
101: /* Did not get DCE, now check the corrected data */
102: if ((actual != dpat) && prt_flg ) {
103: *mcr = 0xc0; /* Turn OFF ECC, clear err.*/
104: writes("\nError in corrected data.");
105: writes("\nExpected : "); writeh(dpat);
106: writes(", Actual : "); writeh(actual);
107: writes("\nAddress : "); writeh(addr);
108: writes("\nNumber Longwords passed ");
109: writed(wcnt); writes("\n");
110: if (loop_flg) goto repeat;
111: else if (hlt_flg) Halt();
112: }
113: }
114: }
115: *mcr = oldstatus; /* old status */
116: }
117:
118: wr_mibreg()
119: {
120: writes("\n\tBuser par0 (MER) : "); writeh(ber2);
121: writes("\n\tBuser par1 (MCBR) : "); writeh(ber1);
122: writes("\n");
123: }
124:
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