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Power 6/32 Unix version 1.2b

#include "definitions"
#define	BEVEC	128			/* offset in scb block for Bus error*/
#define	ecczero	0x00000028
#define	eccone	0x0000012d
#define MEMUNIT 64 * 1024
#include "test4.h"

extern struct OPTIONS OPTIONS;
extern	long	maxmem,endprog,scb;
extern	long	eccloc(), cycle,test_no,errcnt;
extern	long	loop_flg,hlt_flg,prt_flg;
extern long ber1, ber2;
extern long exp_ecc[];
long abmax;
subtest4()
{
  register long *mcr = (long *)0xffffb000;
  register long *mcbr = (long *)0xffffb008;
  register long delay, *addr, bit, ckbits, dpat;
  long oldstatus, data, code, wcnt, cnt, actual, eccloc();
  char *msg;

	if (OPTIONS.header)
	      writes("\n** Subtest4 : ECC single bit error correction.");
	 oldstatus = *mcr;	 	/* save old status */
	 dpat = 0;
	 ckbits = 0xc;			/* Check bits for data 0 */
	 addr = (long *)abmax - 102400;  /* Only check the last 100k */
	 for(wcnt=0;addr <= (long *)abmax;addr++, wcnt++)  
		{
again:
		/* Write data and known good check bits pattern */
	 	data = dpat;		/* Test data pattern */
		*mcbr = ckbits;		/* Check bits of data 0 */
	 	*mcr = 0xc4;  		/* Turn ON diag_write */ 
		delay = *mcr;
		*addr = data;		/* Write Data with check */
					/* bits taken from MCBR */
		*mcr = 0;		/* Turn OFF Diag_write */
		delay = *mcr;
		code = eccloc(addr);   /* Read back data */
		if ((code == -1) && prt_flg) { 	/* Got an unexpected DCE */
			*mcr = 0xc0;	/* Turn OFF ECC, clear err. */
		  	writes("\nUnexpected DCE.<Diag_wr failed>");
			writes("\nAddress     : "); writeh(addr);
			writes("\nLword count : "); writed(wcnt);
			wr_mibreg();
		  	if (loop_flg) goto again;
		  		else if (hlt_flg) Halt();
		  			else continue;
			}			
		  if ((code == -2) && prt_flg) { 
			*mcr = 0;	/* Turn OFF ECC logic */
		        writes("\nUnexpected Buser.");
			wr_mibreg();
		  	if (loop_flg) goto again;
		  		else if (hlt_flg) Halt();
		  			else continue;
			}
		actual = *addr;		/* Read data back to check */
		if ((actual != data)&& prt_flg) {
			writes("\nDiag_wr failed. Wrong data read back.");
			writes("\nExpected "); writeh(data);
			writes(", Actual "); writeh(actual);
		  	if (loop_flg) goto again;
		  		else if (hlt_flg) Halt();
		  			else continue;
			}
		for(bit=1,cnt=0;cnt<32; bit <<= 1, cnt++) {
repeat:
			/* Write data and known good check bits pattern */
	 		data = dpat;		/* Test data pattern */
			data |= bit;	/* Change 1 bit in data pattern */
			*mcbr = ckbits;		/* Check bits of data 0 */
	 		*mcr = 4;  		/* Turn ON diag_write */ 
			delay = *mcr;
			*addr = data;		/* Write Bad data back */
			*mcr = 0;		/* Turn OFF Diag_write */
			delay = *mcr;
		  	code = ecccor(addr,&actual);   /* Read back data */
		  	if ((code == -1) && prt_flg) {
 				/* Didnot correct bad data */
			  	writes("\nGot DCE with single bit error while correction is enable..");
				writes("\n\tData written : ");
				writeh(data);
				writes("\n\tCheck bits written in MCBR : ");
				writeh(ckbits);
				writes("\n\tAddress  : "); writeh(addr);
				wr_mibreg();
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
			  			else continue;
				}			
		  	if ((code == -2) && prt_flg) { 
			        writes("\nUnexpected Buser");
				wr_mibreg();
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
			  			else continue;
				}
			/* Did not get DCE, now check the corrected data */
			if ((actual != dpat) && prt_flg ) {
			  	*mcr = 0xc0;	/* Turn OFF ECC, clear err.*/
			  	writes("\nError in corrected data.");
				writes("\nExpected : "); writeh(dpat);
				writes(", Actual   : "); writeh(actual);
				writes("\nAddress  : "); writeh(addr);
				writes("\nNumber Longwords passed ");
				writed(wcnt); writes("\n");
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
				}
		}
	}
	*mcr = oldstatus;	 	/* old status */
}

wr_mibreg()
{
       writes("\n\tBuser par0 (MER)  : "); writeh(ber2);
       writes("\n\tBuser par1 (MCBR) : "); writeh(ber1);
       writes("\n");
}

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