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Power 6/32 Unix version 1.2b
/*
This test Ecc Memory bits Test
*/
#include "definitions"
#define BEVEC 128 /* offset in scb block for Bus error*/
#define ecczero 0x00000028
#define eccone 0x0000012d
#define MEMUNIT 64 * 1024
#include "test4.h"
extern struct OPTIONS OPTIONS;
extern long maxmem,endprog,scb;
extern long eccloc(), cycle,test_no,errcnt;
extern long loop_flg,hlt_flg,prt_flg;
extern long ber1, ber2, ber3;
long abmax;
long exp_ecc[32] = {
0x4f,0x4a,0x52,0x54,0x57,0x58,0x5b,0x5d,
0x62,0x64,0x67,0x68,0x6b,0x6d,0x70,0x75,
0x0e,0x0b,0x13,0x15,0x16,0x19,0x1a,0x1c,
0x23,0x25,0x26,0x29,0x2a,0x2c,0x31,0x34
};
subtest5()
{
register long *mcr = (long *)0xffffb000;
register long *mcbr = (long *)0xffffb008;
register long *addr, bit, ckbits, delay;
long oldstatus, data, code, wcnt, cnt, actual, eccloc();
char *msg;
if (OPTIONS.header)
writes("\n** Subtest5 : ECC single (data) bit error detection.");
oldstatus = *mcr; /* save old status */
ckbits = 0xc; /* Check bits for data 0 */
addr = (long *)abmax - 102400; /* Only check the last 100k */
for(wcnt=0;addr <= (long *)abmax;addr++, wcnt++)
{
again:
/* Write data and known good check bits pattern */
data = 0; /* Test data pattern */
*mcbr = ckbits; /* Check bits of data 0 */
*mcr = 0xc4; /* Turn ON diag_write */
delay = *mcr;
*addr = data; /* Write Data with check */
/* bits taken from MCBR */
*mcr = 0; /* Turn OFF Diag_write */
delay = *mcr;
code = eccloc(addr); /* Read back data */
if ((code == -1) && prt_flg) { /* Got an unexpected DCE */
*mcr = 0xc0; /* Turn OFF ECC, clear err. */
writes("\nUnexpected DCE.<Diag_wr failed>");
writes("\nAddress : ");writeh(addr);
writes("\nLword count : "); writed(wcnt);
wr_mibreg();
if (loop_flg) goto again;
else if (hlt_flg) Halt();
else continue;
}
if ((code == -2) && prt_flg) {
*mcr = 0; /* Turn OFF ECC logic */
writes("\nUnexpected Buser.");
wr_mibreg();
if (loop_flg) goto again;
else if (hlt_flg) Halt();
else continue;
}
actual = *addr; /* Read data back to check */
if ((actual != data) && prt_flg) {
writes("\nDiag_wr failed. Wrong data read back.");
writes("\nExpected "); writeh(data);
writes(", Actual "); writeh(actual);
if (loop_flg) goto again;
else if (hlt_flg) Halt();
else continue;
}
for(bit=1,cnt=0;cnt<32; bit <<= 1, cnt++) {
repeat:
/* Write data and known good check bits pattern */
data = 0; /* Test data pattern */
data |= bit; /* Change 1 bit in data pattern */
*mcbr = ckbits; /* Check bits of data 0 */
*mcr = 0xc4; /* Turn ON diag_write */
delay = *mcr;
*addr = data; /* Write Bad data back */
*mcr = 0; /* Turn OFF Diag_write */
delay = *mcr;
code = eccloc(addr); /* Read back data */
if ((!code) && prt_flg) { /* Didnot detect bad data */
writes("\nECC failed to detect bad data.");
writes("\n\tAddress : ");
writeh(addr);
writes("\n\tData written : ");
writeh(data);
writes("\n\tCheck bits written to MCBR : ");
writeh(ckbits);
writes("\n\tData read : ");
writeh(ber2);
writes("\n\tMCR after the Read : ");
writeh(ber1);
writes("\n\tMCBR after the Read : ");
writeh(ber3);
writes("\n");
if (loop_flg) goto repeat;
else if (hlt_flg) Halt();
else continue;
}
if ((code == -2) && prt_flg) {
writes("\nUnexpected Buser");
wr_mibreg();
if (loop_flg) goto repeat;
else if (hlt_flg) Halt();
else continue;
}
/* Got the expected DCE, now check syndrome bits */
actual = (tmp_mcbr >> 23) & 0x7f;
if ((actual != exp_ecc[cnt]) && prt_flg ) {
*mcr = 0xc0; /* Turn OFF ECC, clear err.*/
msg = "\nSyndrome Bits error.";
writes("\n\tMCBR : "); writeh(ber1);
error4(msg,addr,exp_ecc[bit-1],actual);
writes("\n\t Data written : ");
writeh(data);
writes("\n\t Check bits written in MCBR : ");
writeh(ckbits);
writes("\nNumber Lwords passed ");
writed(wcnt); writes("\n");
if (loop_flg) goto repeat;
else if (hlt_flg) Halt();
}
}
}
*mcr = oldstatus; /* old status */
}
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