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Power 6/32 Unix version 1.2b

/* 
	This test Ecc Memory bits  Test
*/
#include "definitions"
#define	BEVEC	128			/* offset in scb block for Bus error*/
#define	ecczero	0x00000028
#define	eccone	0x0000012d
#define MEMUNIT 64 * 1024
#include "test4.h"

extern struct OPTIONS OPTIONS;
extern	long	maxmem,endprog,scb;
extern	long	eccloc(), cycle,test_no,errcnt;
extern	long	loop_flg,hlt_flg,prt_flg;
extern long ber1, ber2;

subtest6()
{
  register long *mcr = (long *)0xffffb000;
  register long *mer = (long *)0xffffb020;
  register long *mcbr = (long *)0xffffb008;
  register long *addr, bit, delay;
  long counter, oldstatus, data, code, wcnt, cnt, actual, eccloc();
  char *msg;

	if (OPTIONS.header)
	      writes("\n** Subtest6 : ECC single (check) bit error detection.");
	 oldstatus = *mcr;	 	/* save old status */
	 data = ecczero;		/* data to force a zero ecc */
	 addr = (long *)(((int )endprog + MEMUNIT) & 0xffff0000);
	 counter = 0;
	 for(wcnt=0;addr <= (long *)maxmem;addr++, wcnt++)  
		{
		if (++counter == 5120) {
			counter = 0;
			writes(".");
			}
		for(bit=1,cnt=7;(cnt--); bit <<= 1) {
repeat:
	 		*mcr = 4;  		/* Turn ON diag_write */ 
			*mcbr = 0;		/* Clear check bits in MCBR */
			*addr = data;		/* Write Data with check */
						/* bits taken from MCBR */
			*mcr = 0x1;		/* Turn ON ECC detection */
			delay = *mcr;
			actual = *addr;		/* Read data back */
			*mcr = 0x80;		/* Turn OFF ECC,clear error */
			delay = *mcr;
			if (actual != data) {   /* check data  */
			  	msg = "\nData Bits Test with ECC diagnostic Write enable";
			  	error4(msg,addr,data,actual);
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
				}
			*mcbr = bit;		/* Set check bits in MCBR */
	 		*mcr = 4;  		/* Turn ON diag_write */ 
			delay = *mcr;
			*addr = data;		/* Write data with check */
						/* bits from MCBR */
	 		*mcr = 0;  		/* Turn OFF diag_write */ 
			delay = *mcr;
		  	code = eccloc(addr);   /* Read back data, exp. buser */

		  	if (!code) { 
				*mcr = 0;	/* Turn OFF ECC logic */
			  	writes("\nExpected BUSER didnot happen");
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
			  			else continue;
				}			
		  	if (code == -2) { 
				*mcr = 0;	/* Turn OFF ECC logic */
			        writes("\nWrong Buser parameter,DCE expected");
			        wr_mibreg();
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
			  			else continue;
				}			
			actual = (tmp_mcbr >> 23) & 0x7f;
			if ((actual != bit) && prt_flg ) {
			  	*mcr = 0;	/* Turn OFF ECC logic */
			  	msg = "\nSyndrome Bits error <Check Bits>";
			        wr_mibreg();
			  	error4(msg,addr,bit,actual);
				writes("\nNumber Lwords passed ");
				writed(wcnt); writes("\n");
			  	if (loop_flg) goto repeat;
			  		else if (hlt_flg) Halt();
				}
			*addr = data;      	/* reset test cell */
			for(delay=0x100;(delay>0);--delay);
		}
	}
	*mcr = oldstatus;	 	/* old status */
}


error4(msg,addr,exp,actual)
char *msg;
long addr, actual;
{
	writes(msg);
	writes("\n      Test    Address   Expected    Actual    Count   Cycle \n");
	writes("   ");
	pt_hex(test_no,8);writes("  ");
	pt_hex(addr,8);writes("   ");
	pt_hex(exp,8);writes("  ");
	pt_hex(actual,8);writes("  ");
	pt_hex(errcnt++,8);writes(" ");
	pt_hex(cycle,8);
	locate(addr,exp,actual);
}

Halt()
{
	asm("halt");
}

/*
	Routine to Init. memory + ECC
*/
long I_ecc = 0;
i_ecc()
{
  register long *mcr = (long *)0xffffb000;
  register long *mcbr = (long *)0xffffb008;
  register long *addr, delay;

	 if (I_ecc) return;
		else I_ecc=1;
	 writes("\nInitializing memory + ECC..\n");
	 addr = (long *)(((int )endprog + MEMUNIT) & 0xffff0000);
	 for(;addr <= (long *)maxmem;addr++)  {  
		*mcbr = 0xc;		/* Valid check bits for data 0 */
	 	*mcr = 4;  		/* Turn ON diag_write */ 
		*addr = 0;	/* Write Data with check bit from MCBR */
	 	*mcr = 0;  		/* Turn OFF diag_write */ 
		for(delay=0x5;(delay>0);--delay);
		}
	 *mcr = 0;  			/* Turn OFF diag_write */ 
	 writes("Done..\n");
}

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