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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman|
Return to ac_prot.s CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman |
Power 6/32 Unix version 1.2b
LL0:
.data
.set SBR,0
.set SLR,1
.set P0BR,2
.set P0LR,3
.set P1BR,4
.set P1LR,5
.set P2BR,6
.set P2LR,7
.set IPL,8
.set MAPEN,9
.set MME,9
.set TBIA,10
.set TBIS,11
.set DCK,12
.set CCK,13
.set PCBB,14
.set KSP,19
.set USP,20
.set CPMDCB,21
.set PADC,25
.set DCR,27
.set DC_ON,1
.set DC_OFF,2
.set TB_ON,256
.set TB_OFF,512
.comm _Failpc,4
.comm _test_va,4
.comm _Tpsl,4
.text
.align 1
.globl _protect
_protect:
.word L33
#
# #include "definitions"
#
# extern long iob0, iob1, iob2, iob3, ss1;
# extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7;
# extern long *p_ptr, exp_par0, exp_par1, exp_par2, exp_par3;
#
# long Failpc, test_va, Tpsl;
#
# /* This test will test access protections on PTE in TAHOE memory
# management scheme.
# The main loop of the test running in USER space, KERNEL privilege.
# */
#
# protect()
# { long *temp, pg_no, pte, saved_pte, pte_sys, pte_p0, pte_p1, pte_p2;
jbr L35
L36:
#
# if (ss1) writes("** Subtest2 : Access protection fault\n");
tstl _ss1
jeql L37
.data 1
L39:
.ascii "** Subtest2 : Access protection fault\12\0"
.text
pushl $L39
callf $8,_writes
# pg_no = 0;
L37:
clrl -60(fp)
# asm("mfpr $SBR,_savvec4");
mfpr $SBR,_savvec4
# savvec4 |= 0xc0000000;
orl2 $-1073741824,_savvec4
# asm("mtpr _savvec4,$P0BR"); /* Double map P0 into System space */
mtpr _savvec4,$P0BR
# asm("mfpr $SLR,_savvec4");
mfpr $SLR,_savvec4
# asm("mtpr _savvec4,$P0LR");
mtpr _savvec4,$P0LR
#
# asm("mtpr $3,$DCK");
mtpr $3,$DCK
# asm("mtpr $0,$TBIA");
mtpr $0,$TBIA
# asm("mtpr $0,$PADC");
mtpr $0,$PADC
# asm("mtpr $1,$MME");
mtpr $1,$MME
# asm("jmp *$0f"); /* Go virtual */
jmp *$0f
# asm("0:");
0:
#
# /* Set up SPT */
# pg_no = TEST_PTESYS; /* Map 1st unused PTE to */
movl _unused,-60(fp)
# pte = IOB0; /* physical page iob0 (22) */
andl3 $1073740800,$_iob0,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,-64(fp)
# fixpfn_pte(SBR,pg_no, &pte_sys, pte);
pushl -64(fp)
subl3 $72,fp,r0
pushl r0
pushl -60(fp)
pushl $0
callf $20,_fixpfn_pte
#
# /* Set up P0PT */
# pg_no = TEST_PTEP0; /* Map PTE. 60 in P0PT */
movl $68,-60(fp)
# pte = IOB1; /* physical page iob1 (23) */
andl3 $1073740800,$_iob1,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,-64(fp)
# fixpfn_pte(P0BR,pg_no, &pte_p0, pte);
pushl -64(fp)
subl3 $76,fp,r0
pushl r0
pushl -60(fp)
pushl $2
callf $20,_fixpfn_pte
#
# /* Set up P1PT */
# temp = &u0p1pt; /* Map PTE. 0 in P1PT */
movl $_u0p1pt,-56(fp)
# *temp = IOB2; /* physical page iob2 (24) */
andl3 $1073740800,$_iob2,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,*-56(fp)
# savvec4 = ((long)temp) | SADDR;
orl3 $-1073741824,-56(fp),r0
movl r0,_savvec4
# asm("mtpr _savvec4,$P1BR");
mtpr _savvec4,$P1BR
# asm("mtpr $1,$P1LR");
mtpr $1,$P1LR
#
# /* Set up P2PT */
# temp = &u0p2pt; /* Map PTE. 0 in P2PT */
movl $_u0p2pt,-56(fp)
# *temp = IOB3; /* physical page iob3 (25) */
andl3 $1073740800,$_iob3,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,*-56(fp)
# savvec4 = ((long)temp) | SADDR;
orl3 $-1073741824,-56(fp),r0
movl r0,_savvec4
# savvec4 -= (LAST_VPGNO << 2);
subl2 $4194300,_savvec4
# asm("mtpr _savvec4, $P2BR");
mtpr _savvec4, $P2BR
# asm("mtpr $0xffffe, $P2LR"); /* Use only 1 entry */
mtpr $0xffffe, $P2LR
#
# /* Map test area to allow USER to execute code */
# asm("movab rd_access,_savvec4");
movab rd_access,_savvec4
# pg_no = (savvec4 >> PGSHIFT) & 0xfffff;
shar $10,_savvec4,r0
andl2 $1048575,r0
movl r0,-60(fp)
# fixpv_pte(SBR, pg_no, &saved_pte, PTE_UW | PTE_V);
pushl $-134217728
subl3 $68,fp,r0
pushl r0
pushl -60(fp)
pushl $0
callf $20,_fixpv_pte
# fixpv_pte(SBR, pg_no+1, &saved_pte, PTE_UW | PTE_V);
pushl $-134217728
subl3 $68,fp,r0
pushl r0
addl3 $1,-60(fp),r0
pushl r0
pushl $0
callf $20,_fixpv_pte
#
# prot(); /* Do test .. */
callf $4,_prot
#
# fixpv_pte(SBR, pg_no, &saved_pte, PTE_KW | PTE_V);
pushl $-536870912
subl3 $68,fp,r0
pushl r0
pushl -60(fp)
pushl $0
callf $20,_fixpv_pte
# fixpv_pte(SBR, pg_no+1, &saved_pte, PTE_KW | PTE_V);
pushl $-536870912
subl3 $68,fp,r0
pushl r0
addl3 $1,-60(fp),r0
pushl r0
pushl $0
callf $20,_fixpv_pte
#
# /* Restore original PTEs */
# pg_no = TEST_PTESYS;
movl _unused,-60(fp)
# pte = IOB0;
andl3 $1073740800,$_iob0,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,-64(fp)
# fixpfn_pte(SBR,pg_no, &pte_sys, pte_sys&0x3fffff);
andl3 $4194303,-72(fp),r0
pushl r0
subl3 $72,fp,r0
pushl r0
pushl -60(fp)
pushl $0
callf $20,_fixpfn_pte
# pg_no = TEST_PTEP0;
movl $68,-60(fp)
# pte = IOB1;
andl3 $1073740800,$_iob1,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,-64(fp)
# fixpfn_pte(P0BR,pg_no, &pte_p0, pte_p0&0x3fffff);
andl3 $4194303,-76(fp),r0
pushl r0
subl3 $76,fp,r0
pushl r0
pushl -60(fp)
pushl $2
callf $20,_fixpfn_pte
# pg_no = TEST_PTEP1;
clrl -60(fp)
# pte = IOB2;
andl3 $1073740800,$_iob2,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,-64(fp)
# fixpfn_pte(P1BR,pg_no, &pte_p1, pte_p1&0x3fffff);
andl3 $4194303,-80(fp),r0
pushl r0
subl3 $80,fp,r0
pushl r0
pushl -60(fp)
pushl $4
callf $20,_fixpfn_pte
# pg_no = TEST_PTEP2;
movl $1048575,-60(fp)
# pte = IOB3;
andl3 $1073740800,$_iob3,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,-64(fp)
# fixpfn_pte(P2BR,pg_no, &pte_p2, pte_p2&0x3fffff);
andl3 $4194303,-84(fp),r0
pushl r0
subl3 $84,fp,r0
pushl r0
pushl -60(fp)
pushl $6
callf $20,_fixpfn_pte
#
# asm("mtpr $0,$MME"); /* Back to physical */
mtpr $0,$MME
# asm("mtpr $0,$P0LR"); /* Invalidate P0BR */
mtpr $0,$P0LR
# }
ret
.set L33,0x0
L35:
subl3 $84,fp,sp
jbr L36
.data
.text
.align 1
.globl _prot
_prot:
.word L43
#
# prot()
# { long access_md, privilege, exp_int;
jbr L45
L46:
#
#
# /* PTE : No Access */
# access_md = PTE_NOACC | PTE_V;
movl $-2147483648,-56(fp)
# /* Try all privileges with R/W access on all tables */
# exp_int = TRUE;
movl $1,-64(fp)
# for(privilege=USER; privilege>=KERNEL; privilege--)
movl $1,-60(fp)
L49:
tstl -60(fp)
jlss L48
# chmaps_prot(access_md,privilege,"rw",exp_int);
.data 1
L51:
.ascii "rw\0"
.text
pushl -64(fp)
pushl $L51
pushl -60(fp)
pushl -56(fp)
callf $20,_chmaps_prot
L47:
decl -60(fp)
jbr L49
L48:
#
# /* PTE : Kernel Read */
# access_md = PTE_KR | PTE_V;
movl $-1073741824,-56(fp)
# chmaps_prot(access_md,USER,"rw",exp_int);
.data 1
L52:
.ascii "rw\0"
.text
pushl -64(fp)
pushl $L52
pushl $1
pushl -56(fp)
callf $20,_chmaps_prot
# chmaps_prot(access_md,KERNEL,"w",exp_int);
.data 1
L53:
.ascii "w\0"
.text
pushl -64(fp)
pushl $L53
pushl $0
pushl -56(fp)
callf $20,_chmaps_prot
# exp_int = FALSE;
clrl -64(fp)
# chmaps_prot(access_md,KERNEL,"r",exp_int);
.data 1
L54:
.ascii "r\0"
.text
pushl -64(fp)
pushl $L54
pushl $0
pushl -56(fp)
callf $20,_chmaps_prot
#
# /* PTE : Kernel Write */
# access_md = PTE_KW | PTE_V;
movl $-536870912,-56(fp)
# exp_int = TRUE;
movl $1,-64(fp)
# chmaps_prot(access_md,USER,"rw",exp_int);
.data 1
L55:
.ascii "rw\0"
.text
pushl -64(fp)
pushl $L55
pushl $1
pushl -56(fp)
callf $20,_chmaps_prot
# exp_int = FALSE;
clrl -64(fp)
# chmaps_prot(access_md,0,"rw",exp_int);
.data 1
L56:
.ascii "rw\0"
.text
pushl -64(fp)
pushl $L56
pushl $0
pushl -56(fp)
callf $20,_chmaps_prot
#
#
# /* PTE : User Read/Kernel Read */
# access_md = PTE_URKR | PTE_V;
movl $-805306368,-56(fp)
# exp_int = TRUE;
movl $1,-64(fp)
# chmaps_prot(access_md,USER,"w",exp_int);
.data 1
L57:
.ascii "w\0"
.text
pushl -64(fp)
pushl $L57
pushl $1
pushl -56(fp)
callf $20,_chmaps_prot
# chmaps_prot(access_md,KERNEL,"w",exp_int);
.data 1
L58:
.ascii "w\0"
.text
pushl -64(fp)
pushl $L58
pushl $0
pushl -56(fp)
callf $20,_chmaps_prot
# exp_int = FALSE;
clrl -64(fp)
# chmaps_prot(access_md,USER,"r",exp_int);
.data 1
L59:
.ascii "r\0"
.text
pushl -64(fp)
pushl $L59
pushl $1
pushl -56(fp)
callf $20,_chmaps_prot
# chmaps_prot(access_md,KERNEL,"r",exp_int);
.data 1
L60:
.ascii "r\0"
.text
pushl -64(fp)
pushl $L60
pushl $0
pushl -56(fp)
callf $20,_chmaps_prot
#
#
# /* PTE : User Read/ Kernel Read/Write */
# access_md = PTE_URKW | PTE_V;
movl $-268435456,-56(fp)
# exp_int = TRUE;
movl $1,-64(fp)
# chmaps_prot(access_md,USER,"w",exp_int);
.data 1
L61:
.ascii "w\0"
.text
pushl -64(fp)
pushl $L61
pushl $1
pushl -56(fp)
callf $20,_chmaps_prot
# exp_int = FALSE;
clrl -64(fp)
# chmaps_prot(access_md,USER,"r",exp_int);
.data 1
L62:
.ascii "r\0"
.text
pushl -64(fp)
pushl $L62
pushl $1
pushl -56(fp)
callf $20,_chmaps_prot
# chmaps_prot(access_md,KERNEL,"rw",exp_int);
.data 1
L63:
.ascii "rw\0"
.text
pushl -64(fp)
pushl $L63
pushl $0
pushl -56(fp)
callf $20,_chmaps_prot
#
# /* PTE : User Read/Write/ Kernel Read/Write */
# access_md = PTE_UW | PTE_V;
movl $-134217728,-56(fp)
# exp_int = FALSE;
clrl -64(fp)
# for(privilege=USER; privilege>=KERNEL; privilege--)
movl $1,-60(fp)
L66:
tstl -60(fp)
jlss L65
# chmaps_prot(access_md,privilege,"rw",exp_int);
.data 1
L67:
.ascii "rw\0"
.text
pushl -64(fp)
pushl $L67
pushl -60(fp)
pushl -56(fp)
callf $20,_chmaps_prot
L64:
decl -60(fp)
jbr L66
L65:
#
# }
ret
.set L43,0x0
L45:
subl3 $64,fp,sp
jbr L46
.data
.comm _spc_str,4
.text
.align 1
.globl _chmaps_prot
_chmaps_prot:
.word L69
#
# char *spc_str;
#
# chmaps_prot(access_md,priv,run_access,exp_int)
# long access_md, priv, exp_int;
# char *run_access;
# { long pg_table, pte_no, space;
jbr L71
L72:
#
# for (pg_table=SBR; pg_table<=P2BR; pg_table += 2)
clrl -56(fp)
L75:
cmpl -56(fp),$6
jgtr L74
# {
# if (pg_table == SBR) {
tstl -56(fp)
jneq L76
# pte_no = TEST_PTESYS;
movl _unused,-60(fp)
# space = SADDR; }
movl $-1073741824,-64(fp)
# if (pg_table == P0BR) {
L76:
cmpl -56(fp),$2
jneq L77
# pte_no = TEST_PTEP0;
movl $68,-60(fp)
# space = P0ADDR; }
clrl -64(fp)
# if (pg_table == P1BR) {
L77:
cmpl -56(fp),$4
jneq L78
# pte_no = TEST_PTEP1;
clrl -60(fp)
# space = P1ADDR; }
movl $1073741824,-64(fp)
# if (pg_table == P2BR) {
L78:
cmpl -56(fp),$6
jneq L79
# pte_no = TEST_PTEP2;
movl $1048575,-60(fp)
# space = P2ADDR; }
movl $-2147483648,-64(fp)
# force_flt(pg_table,pte_no,access_md,priv,run_access,space,exp_int);
L79:
pushl 16(fp)
pushl -64(fp)
pushl 12(fp)
pushl 8(fp)
pushl 4(fp)
pushl -60(fp)
pushl -56(fp)
callf $32,_force_flt
# }
L73:
addl2 $2,-56(fp)
jbr L75
L74:
# }
ret
.set L69,0x0
L71:
subl3 $64,fp,sp
jbr L72
.data
.text
.align 1
.globl _force_flt
_force_flt:
.word L81
#
# /* This routine forces protection faults with read and write access
# to page table specified by tbl_no . The access bits of this PTE
# is set to value of pte_access, the process that access this PTE
# is running in the mode specified by rum_mode.
# tbl_no : (0,1,2,3) corresponding to P0PT, P1PT, P2PT, SPT.
# which_pte : PTE to be accessed
# pte_access : valid and protection bits to be set on PTE
# access : "r", "rw", "w"/ "R", "RW", "W"
# run_mode : privilege of process when access PTE
# */
#
# force_flt(tbl_no, which_pte, pte_access, run_mode, access, addr_space, exp_int)
# long tbl_no, which_pte, pte_access, run_mode, addr_space, exp_int;
# char *access;
# {
jbr L83
L84:
# long *st_base, saved_vec1,saved_vec2,saved_pte,test_adr,tflag;
# long ix, handler_adr;
# char *acc_str, *pmode_str;
#
# /* Set protection bits of target PTE */
# fixpv_pte(tbl_no,which_pte,&saved_pte,pte_access);
pushl 12(fp)
subl3 $68,fp,r0
pushl r0
pushl 8(fp)
pushl 4(fp)
callf $20,_fixpv_pte
#
# /* Get virtual address of test location */
# test_adr = (which_pte<<PGSHIFT)|addr_space;
shll $10,8(fp),r0
orl2 24(fp),r0
movl r0,-72(fp)
#
# for(ix=0;ix<2;ix++)
clrl -80(fp)
L87:
cmpl -80(fp),$2
jgeq L86
# {
# if (access[ix]==NULL) break;
movl 20(fp),r0
movl -80(fp),r1
tstb (r0)[r1]
jneq L88
jbr L86
# /* Set handler of protection fault */
# if (exp_int==TRUE)
L88:
cmpl 28(fp),$1
jneq L89
# asm("movab pro_flt1,_savvec4");
movab pro_flt1,_savvec4
# else
jbr L90
L89:
# asm("movab pro_flt2,_savvec4");
movab pro_flt2,_savvec4
L90:
# handler_adr = savvec4;
movl _savvec4,-84(fp)
# set_handler(PROT_VEC,&saved_vec1,handler_adr);
pushl -84(fp)
subl3 $60,fp,r0
pushl r0
pushl $47
callf $16,_set_handler
#
# /* Set handler for DATA ALIGNMENT FAULT */
# asm("movab chmk_hd,_savvec4");
movab chmk_hd,_savvec4
# handler_adr = savvec4;
movl _savvec4,-84(fp)
# set_handler(ALIGN_FLT,&saved_vec2,handler_adr);
pushl -84(fp)
subl3 $64,fp,r0
pushl r0
pushl $53
callf $16,_set_handler
#
# /* Set expected parameter words */
# exp_par1 = exp_par2 = exp_par3 = 0;
clrl _exp_par3
movl _exp_par3,r0
movl r0,_exp_par2
movl _exp_par2,r0
movl r0,_exp_par1
# exp_par1 = test_adr;
movl -72(fp),_exp_par1
# if ((access[ix]=='r') || (access[ix]=='R'))
movl 20(fp),r0
movl -80(fp),r1
cmpb (r0)[r1],$114
jeql L9999
movl 20(fp),r0
movl -80(fp),r1
cmpb (r0)[r1],$82
jneq L92
L9999:
# { /* protection violation, read access */
# asm("movab rd_access,_exp_par2"); /* Expected PC */
movab rd_access,_exp_par2
# exp_par0 = 0;
clrl _exp_par0
# }
# else
jbr L93
L92:
# { /* protection violation, write access */
# asm("movab wr_access,_exp_par2");
movab wr_access,_exp_par2
# exp_par0 = 4;
movl $4,_exp_par0
# }
L93:
#
# asm("mtpr $0xbfffb3fc,$USP"); /* Set up user stack */
mtpr $0xbfffb3fc,$USP
# asm("movab (sp),_savvec5");
movab (sp),_savvec5
# savvec5 -= 40; /* KSP is 10 longword after ISP */
subl2 $40,_savvec5
# asm("mtpr _savvec5,$KSP");
mtpr _savvec5,$KSP
#
# /* set up to change privilege */
# exp_par3 = run_mode << 24;
shll $24,16(fp),r0
movl r0,_exp_par3
# Tpsl = exp_par3; /* PSL when force fault */
movl _exp_par3,_Tpsl
# Failpc = exp_par2; /* PC to force fault */
movl _exp_par2,_Failpc
# asm("pushl _exp_par3");
pushl _exp_par3
# asm("pushl _exp_par2"); /* Push PSL, PC on current stack */
pushl _exp_par2
#
# /* Change mode */
# test_va = savvec5 = test_adr;
movl -72(fp),_savvec5
movl _savvec5,r0
movl r0,_test_va
# asm("movl _savvec5,r0");
movl _savvec5,r0
#
# /* Enable false */
# asm("mtpr $64,$DCR");
mtpr $64,$DCR
# asm("rei"); /* Go : Amem ... */
rei
# asm("halt"); /* REI fails ... */
halt
#
# asm("rtn0_p0:");
rtn0_p0:
# asm("movl r0,_savvec5"); /* flag indicate where return from */
movl r0,_savvec5
# tflag = savvec5;
movl _savvec5,-76(fp)
# st_base = &scb;
movl $_scb,-56(fp)
#
# /* Restore Prot_fault, ALIGN_FLT vectors */
# *(st_base + PROT_VEC) = saved_vec1;
movl -56(fp),r0
movl -60(fp),188(r0)
# *(st_base + ALIGN_FLT) = saved_vec2;
movl -56(fp),r0
movl -64(fp),212(r0)
#
# if (tflag && exp_int)
tstl -76(fp)
jeql L94
tstl 28(fp)
jeql L94
# { /* Error : expected event did not happen */
# writes("** Expected protection fault didnot occured\n");
.data 1
L95:
.ascii "** Expected protection fault didnot occured\12\0"
.text
pushl $L95
callf $8,_writes
# ac_error1();
callf $4,_ac_error1
# asm("halt");
halt
# }
#
# /* check fault parameters pushed on stack */
# if ((exp_int==TRUE)&&(tflag==FALSE)) chk_fpars("");
L94:
cmpl 28(fp),$1
jneq L97
tstl -76(fp)
jneq L97
.data 1
L99:
.ascii "\0"
.text
pushl $L99
callf $8,_chk_fpars
# }
L97:
L85:
incl -80(fp)
jbr L87
L86:
#
# /* Restore tested PTE's */
# savvec5 = tbl_no;
movl 4(fp),_savvec5
# asm("mfpr _savvec5,_savvec6");
mfpr _savvec5,_savvec6
# st_base = (long *)savvec6;
movl _savvec6,-56(fp)
# st_base += which_pte;
shll $2,8(fp),r0
addl2 r0,-56(fp)
# *st_base = saved_pte;
movl -68(fp),*-56(fp)
# }
ret
.set L81,0x0
L83:
subl3 $92,fp,sp
jbr L84
.data
.text
.align 1
.globl _ptfx_handler
_ptfx_handler:
.word L101
#
#
# /* Handler of protection fault exception. */
# ptfx_handler()
# {
jbr L103
L104:
# asm(".align 2");
.align 2
# asm("pro_flt1:"); /* EXPECTED INTERRUPT */
pro_flt1:
#
# asm("mtpr $0x1f,$IPL");
mtpr $0x1f,$IPL
# asm("movab (sp),_savvec5"); /* set pointer to parameters */
movab (sp),_savvec5
# p_ptr = (long *)savvec5;
movl _savvec5,_p_ptr
# asm("svpctx"); /* switch back to ISP */
svpctx
# asm("clrl r0");
clrl r0
# asm("jmp rtn0_p0"); /* return to test */
jmp rtn0_p0
#
# asm(".align 2");
.align 2
# asm("pro_flt2:"); /* UNEXPECTED INTERRUPT */
pro_flt2:
# asm("mtpr $0x1f,$IPL");
mtpr $0x1f,$IPL
# asm("movab (sp),_savvec5"); /* set pointer to parameters */
movab (sp),_savvec5
# asm("movl fp,_saved_fp"); /* save fp */
movl fp,_saved_fp
# asm("movab (sp),fp"); /* set new frame pointer for next CALLS */
movab (sp),fp
# p_ptr = (long *)savvec5;
movl _savvec5,_p_ptr
#
# writes("** Unexpected protection fault\n");
.data 1
L105:
.ascii "** Unexpected protection fault\12\0"
.text
pushl $L105
callf $8,_writes
# ac_error1();
callf $4,_ac_error1
# prt_par("** Parameters : ",p_ptr); /* print fault parameters */
.data 1
L107:
.ascii "** Parameters : \0"
.text
pushl _p_ptr
pushl $L107
callf $12,_prt_par
# asm("svpctx"); /* switch back to ISP */
svpctx
# asm("clrl r0");
clrl r0
# asm("movl _saved_fp,fp"); /* restore fp */
movl _saved_fp,fp
# asm("halt");
halt
# asm("jmp rtn0_p0"); /* return to test */
jmp rtn0_p0
# }
ret
.set L101,0x0
L103:
jbr L104
.data
.text
.align 1
.globl _chmk_handler
_chmk_handler:
.word L109
#
# chmk_handler()
# {
jbr L111
L112:
# asm(".align 2");
.align 2
# asm("chmk_hd:"); /* Come here by causing a data not align fault */
chmk_hd:
# /* return to test */
# asm("mtpr $0x1f,$IPL"); /* Set IPL to HIGH */
mtpr $0x1f,$IPL
# asm("svpctx"); /* switch back to ISP */
svpctx
# asm("movl $1,r0"); /* set flag to indicate return from here */
movl $1,r0
# asm("jmp rtn0_p0");
jmp rtn0_p0
# }
ret
.set L109,0x0
L111:
jbr L112
.data
.text
.align 1
.globl _TEST_AREA
_TEST_AREA:
.word L114
#
# TEST_AREA()
# {
jbr L116
L117:
#
# asm("rd_access:");
rd_access:
# asm("movl (r0),r12"); /* should cause protection fault exception !! */
movl (r0),r12
#
# /* Get back KERNEL privilege by causing a data not align fault */
# asm("movl align_f,r10");
movl align_f,r10
# asm("halt"); /* otherwise HALT .... */
halt
#
# asm("wr_access:");
wr_access:
# asm("movl $1,(r0)"); /* should cause protection fault exception !! */
movl $1,(r0)
#
# /* Get back KERNEL privilege by causing a data not align fault */
# asm("movl align_f,r10");
movl align_f,r10
# asm("halt"); /* otherwise HALT .... */
halt
# asm(".align 1"); /* Word align */
.align 1
# asm("align_f:");
align_f:
# asm(".long 0");
.long 0
# }
ret
.set L114,0x0
L116:
jbr L117
.data
.text
.align 1
.globl _prt_par
_prt_par:
.word L118
#
# /* Print fault parameters of memory management exceptions */
# prt_par(str,par)
# char *str;
# long *par;
# {
jbr L120
L121:
# writes(str);
pushl 4(fp)
callf $8,_writes
# writeh(*par++); writes(" ");
movl 8(fp),r0
addl2 $4,8(fp)
pushl (r0)
callf $8,_writeh
.data 1
L123:
.ascii " \0"
.text
pushl $L123
callf $8,_writes
# writeh(*par++); writes(" ");
movl 8(fp),r0
addl2 $4,8(fp)
pushl (r0)
callf $8,_writeh
.data 1
L124:
.ascii " \0"
.text
pushl $L124
callf $8,_writes
# writeh(*par++); writes(" ");
movl 8(fp),r0
addl2 $4,8(fp)
pushl (r0)
callf $8,_writeh
.data 1
L125:
.ascii " \0"
.text
pushl $L125
callf $8,_writes
# writeh(*par); writec('\n');
pushl *8(fp)
callf $8,_writeh
pushl $10
callf $8,_writec
# }
ret
.set L118,0x0
L120:
jbr L121
.data
.text
.align 1
.globl _chk_fpars
_chk_fpars:
.word L127
#
# /* This routine assumes that global pointer p_ptr points to the actual
# parameters pushed on the stack, and exp_par0 is the 1 of the expected
# parameters.
# */
# chk_fpars(msg)
# char *msg;
# { long *pars, *e_pars;
jbr L129
L130:
# long act_param0, act_param1, act_param2, act_param3;
#
# e_pars = &exp_par0; /* pointer to expected parameters */
movl $_exp_par0,-60(fp)
# pars = p_ptr; /* pointer to actual parameters */
movl _p_ptr,-56(fp)
# act_param0 = *pars++;
movl *-56(fp),-64(fp)
addl2 $4,-56(fp)
# act_param1 = *pars++;
movl *-56(fp),-68(fp)
addl2 $4,-56(fp)
# act_param2 = *pars++;
movl *-56(fp),-72(fp)
addl2 $4,-56(fp)
# act_param3 = (*pars) & 0xffffffc0; /* Mask out PSW flags */
andl3 $-64,*-56(fp),r0
movl r0,-76(fp)
# if ((exp_par0 != act_param0) || (exp_par1 != act_param1) ||
# (exp_par2 != act_param2) || (exp_par3 != act_param3)) {
cmpl _exp_par0,-64(fp)
jneq L9998
cmpl _exp_par1,-68(fp)
jneq L9998
cmpl _exp_par2,-72(fp)
jneq L9998
cmpl _exp_par3,-76(fp)
jeql L131
L9998:
# writes(msg);
pushl 4(fp)
callf $8,_writes
# writes("** Error in fault paramters\n");
.data 1
L132:
.ascii "** Error in fault paramters\12\0"
.text
pushl $L132
callf $8,_writes
# ac_error1();
callf $4,_ac_error1
# prt_par("** Expected : ",&exp_par0);
.data 1
L133:
.ascii "** Expected : \0"
.text
pushl $_exp_par0
pushl $L133
callf $12,_prt_par
# prt_par("** Actual : ",p_ptr);
.data 1
L134:
.ascii "** Actual : \0"
.text
pushl _p_ptr
pushl $L134
callf $12,_prt_par
# asm("halt");
halt
# }
# }
L131:
ret
.set L127,0x0
L129:
subl3 $76,fp,sp
jbr L130
.data
.text
.align 1
.globl _ac_error1
_ac_error1:
.word L135
#
# ac_error1()
# {
jbr L137
L138:
# writes("** PC : "); writeh(Failpc); writec('\n');
.data 1
L139:
.ascii "** PC : \0"
.text
pushl $L139
callf $8,_writes
pushl _Failpc
callf $8,_writeh
pushl $10
callf $8,_writec
# writes("** VA : "); writeh(test_va); writec('\n');
.data 1
L140:
.ascii "** VA : \0"
.text
pushl $L140
callf $8,_writes
pushl _test_va
callf $8,_writeh
pushl $10
callf $8,_writec
# writes("** PSL : "); writeh(Tpsl); writec('\n');
.data 1
L141:
.ascii "** PSL : \0"
.text
pushl $L141
callf $8,_writes
pushl _Tpsl
callf $8,_writeh
pushl $10
callf $8,_writec
# prt_base(test_va);
pushl _test_va
callf $8,_prt_base
# }
ret
.set L135,0x0
L137:
jbr L138
.data
#
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