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1.1 ! root 1: ! 2: #include "definitions" ! 3: ! 4: ! 5: extern long iob0, iob1, iob2, iob3, ss1; ! 6: extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7; ! 7: extern long *p_ptr, ret_adr, exp_par0, exp_par1, exp_par2, exp_par3; ! 8: extern long act_par0, act_par1, act_par2, act_par3, saved_psl; ! 9: extern long Failpc, Tpsl , test_va; ! 10: ! 11: /* The purpose of this test is to validate that TAHOE will check access ! 12: protection bits before checking the valid of the PTE . ! 13: This test run in user P0 space ,KERNEL privilege and try to access ! 14: system and P1 space which have corresponding PTE set as : ! 15: Protection bits : Kernel read only ! 16: Valid bit : Off ! 17: */ ! 18: ! 19: ! 20: long trans_excpt; ! 21: ! 22: pv_test() ! 23: { long *pt_ptr; ! 24: ! 25: if (ss1) ! 26: writes("** Subtest5 : order of memory management exceptions\n"); ! 27: pt_ptr = (long *)0; ! 28: asm("mfpr $SBR,_savvec4"); ! 29: savvec4 |= 0xc0000000; /* Make it system virtual address */ ! 30: asm("mtpr _savvec4,$P0BR"); ! 31: asm("mfpr $SLR,_savvec4"); ! 32: asm("mtpr _savvec4,$P0LR"); ! 33: ! 34: asm("mtpr $4,$DCK"); ! 35: asm("mtpr $0,$TBIA"); ! 36: asm("mtpr $0,$PADC"); ! 37: asm("mtpr $1,$MME"); /* Enable MME */ ! 38: asm("jmp *$0f"); /* Go virtual .. */ ! 39: asm("0:"); ! 40: ! 41: vp_tst(IOB0, SBR, SADDR); ! 42: ! 43: /* Set up P1PT */ ! 44: pt_ptr = &u0p1pt; ! 45: *pt_ptr = IOB1; /* 1st PTE of P1 mapped to IOB1 */ ! 46: savvec4 = ((long)pt_ptr) | SADDR; ! 47: asm("mtpr _savvec4,$P1BR"); ! 48: asm("mtpr $1,$P1LR"); ! 49: vp_tst(TEST_PTEP1, P1BR, P1ADDR); ! 50: ! 51: asm("mtpr $0,$MME"); /* Back to physical */ ! 52: asm("mtpr $0,$P0LR"); /* Invalidate P0 space */ ! 53: } ! 54: ! 55: ! 56: vp_tst(test_pte, pg_tbl, space) ! 57: long test_pte, pg_tbl, space; ! 58: { ! 59: long lgword, pfn, saved_vec1, saved_pte, test_adr, access_md; ! 60: long *scb_base0, *scb_base1, saved_vec2, tflag; ! 61: char *msg1, *msg2; ! 62: ! 63: trans_excpt = tflag = 0; ! 64: /* Set v and protection bits of target PTE in SPT */ ! 65: access_md = PTE_NOACC; ! 66: fixpv_pte(pg_tbl,test_pte,&saved_pte,access_md); ! 67: ! 68: /* Set expected parameter words */ ! 69: exp_par0 = 4; /* protection violation, write access */ ! 70: test_adr = ( (test_pte) << PGSHIFT) | space; ! 71: test_va = exp_par1 = test_adr; ! 72: asm("movab sys_wr,_exp_par2"); /* PC at faulting instruction */ ! 73: Failpc = exp_par2; ! 74: exp_par3 = 0; ! 75: ! 76: /* Set handler of protection fault */ ! 77: scb_base0 = scb_base1 = &scb; ! 78: scb_base0 += PROT_VEC; ! 79: saved_vec1 = *scb_base0; /* Save original vector */ ! 80: asm("movab prot_flt4,_savvec4"); ! 81: *scb_base0 = savvec4; /* Set new vector */ ! 82: ! 83: /* Set handler of translation fault */ ! 84: scb_base1 += TRANS_VEC; ! 85: saved_vec2 = *scb_base1; /* Save original vector */ ! 86: asm("movab trans_flt4,_savvec4"); ! 87: *scb_base1 = savvec4; /* Set new vector */ ! 88: ! 89: asm("movpsl _exp_par3"); /* Set expected PSL */ ! 90: exp_par3 &= 0xffffffc0; /* Mask out PSW flags */ ! 91: Tpsl = exp_par3; ! 92: asm("movl _exp_par1,r0"); ! 93: asm("sys_wr:"); ! 94: asm("movl $1,(r0)"); /* Should cause exception right here */ ! 95: tflag++; ! 96: writes("** Expected protection fault did not occur when write\n"); ! 97: if (space==SADDR) ! 98: writes(" to a page in SPT that is No_access and V_bit off\n"); ! 99: else ! 100: writes(" to a page in P1PT that is No_access and V_bit off\n"); ! 101: ac_error1(); ! 102: asm("halt"); ! 103: asm("jmp vp_retpc"); ! 104: ! 105: asm("at_flt:") ! 106: tflag++; ! 107: writes("** Translation fault occured when write to a page \n"); ! 108: if (space==SADDR) ! 109: writes(" in SPT that is No_access and V_bit off\n"); ! 110: else ! 111: writes(" in P1PT that is No_access and V_bit off\n"); ! 112: ac_error1(); ! 113: asm("halt"); ! 114: ! 115: asm("vp_retpc:"); ! 116: *scb_base0 = saved_vec1; /* Restore original vector */ ! 117: *scb_base1 = saved_vec2; ! 118: access_md = saved_pte & 0xf8000000; /* Restore test PTE in SPT */ ! 119: pfn = saved_pte & 0x3fffff; ! 120: fixpfn_pte(SBR,test_pte,&saved_pte,pfn); ! 121: fixpv_pte(SBR,test_pte,&saved_pte,access_md); ! 122: ! 123: if (tflag==0) ! 124: chk_fpars(""); ! 125: } ! 126: ! 127: ! 128: ! 129: ! 130: ptf_handler() ! 131: { ! 132: asm(".align 2"); ! 133: /* Handler of protection fault exception. */ ! 134: asm("prot_flt4:"); ! 135: asm("movab _act_par0,_p_ptr"); /* Set pointer to fault parameters */ ! 136: asm("movl (sp)+,_act_par0"); ! 137: asm("movl (sp)+,_act_par1"); ! 138: asm("movl (sp)+,_act_par2"); ! 139: asm("movl (sp)+,_act_par3"); ! 140: ! 141: /* return to test */ ! 142: if (trans_excpt==0) ! 143: asm("jmp vp_retpc"); ! 144: else ! 145: asm("jmp at_flt"); ! 146: ! 147: asm(".align 2"); ! 148: /* Handler of translation not valid fault. */ ! 149: asm("trans_flt4:"); ! 150: trans_excpt++; /* Set flag */ ! 151: asm("jmp prot_flt4"); ! 152: } ! 153: ! 154:
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