File:  [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman / pv_test.c
Revision 1.1.1.2 (vendor branch): download - view: text, annotated - select for diffs
Sun Jul 28 12:30:49 2019 UTC (7 years ago) by root
Branches: bsd, MAIN
CVS tags: v121, HEAD
Power 6/32 Unix version 1.21


#include "definitions"


extern long iob0, iob1, iob2, iob3, ss1;
extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7;
extern long *p_ptr, ret_adr, exp_par0, exp_par1, exp_par2, exp_par3;
extern long act_par0, act_par1, act_par2, act_par3, saved_psl;
extern long Failpc, Tpsl , test_va;

/* 	The purpose of this test is to validate that TAHOE will check access 
   protection bits before checking the valid of the PTE .
	This test run in user P0 space ,KERNEL privilege and try to access 
   system and P1 space which have corresponding PTE set as : 
		Protection bits : Kernel read only
		Valid bit       : Off
*/


long trans_excpt;

pv_test()
{	long *pt_ptr;
	
	if (ss1) 
		writes("** Subtest5 : order of memory management exceptions\n");
	pt_ptr = (long *)0;
	asm("mfpr $SBR,_savvec4");
	savvec4 |= 0xc0000000;		/* Make it system virtual address */
	asm("mtpr _savvec4,$P0BR");
	asm("mfpr $SLR,_savvec4");
	asm("mtpr _savvec4,$P0LR");

	asm("mtpr $4,$DCK");
	asm("mtpr $0,$TBIA");
	asm("mtpr $0,$PADC");
	asm("mtpr $1,$MME");		/* Enable MME */
	asm("jmp  *$0f");		/* Go virtual .. */
asm("0:");

	vp_tst(IOB0, SBR, SADDR);

	/* Set up P1PT  */
	pt_ptr = &u0p1pt;
	*pt_ptr = IOB1;			/* 1st PTE of P1 mapped to IOB1 */
	savvec4 = ((long)pt_ptr) | SADDR;
	asm("mtpr _savvec4,$P1BR");
	asm("mtpr $1,$P1LR");
	vp_tst(TEST_PTEP1, P1BR, P1ADDR);

	asm("mtpr $0,$MME");		/* Back to physical */
	asm("mtpr $0,$P0LR");		/* Invalidate P0 space */
}


vp_tst(test_pte, pg_tbl, space)
long test_pte, pg_tbl, space;
{
	long lgword, pfn, saved_vec1, saved_pte, test_adr, access_md;
	long *scb_base0, *scb_base1, saved_vec2, tflag;
	char *msg1, *msg2;

	trans_excpt = tflag = 0;
	/* Set v and protection bits of target PTE in SPT */
	access_md = PTE_NOACC;
	fixpv_pte(pg_tbl,test_pte,&saved_pte,access_md); 
	
	/* Set expected parameter words */
	exp_par0 = 4;		/* protection violation, write access */
	test_adr = ( (test_pte) << PGSHIFT) | space;
	test_va = exp_par1 = test_adr;
	asm("movab sys_wr,_exp_par2"); 	/* PC at faulting instruction */
	Failpc = exp_par2;
	exp_par3 = 0;

	/* Set handler of protection fault */
	scb_base0 = scb_base1 = &scb;
	scb_base0 += PROT_VEC;
	saved_vec1 = *scb_base0;		/* Save original vector */
	asm("movab prot_flt4,_savvec4");
	*scb_base0 = savvec4;			/* Set new vector */

	/* Set handler of translation fault */
	scb_base1 += TRANS_VEC;
	saved_vec2 = *scb_base1;		/* Save original vector */
	asm("movab trans_flt4,_savvec4");
	*scb_base1 = savvec4;			/* Set new vector */

	asm("movpsl _exp_par3");	 	/* Set expected PSL */
	exp_par3 &= 0xffffffc0;			/* Mask out PSW flags */
	Tpsl = exp_par3;
	asm("movl _exp_par1,r0");
asm("sys_wr:");
	asm("movl $1,(r0)");		/* Should cause exception right here */
	tflag++;
	writes("** Expected protection fault did not occur when write\n");
	if (space==SADDR)
		writes("   to a page in SPT that is No_access and V_bit off\n");
	   else
	       writes("   to a page in P1PT that is No_access and V_bit off\n");
	ac_error1();
	asm("halt");
	asm("jmp  vp_retpc");

asm("at_flt:");
	tflag++;
	writes("** Translation fault occured when write to a page \n");
	if (space==SADDR)
		writes("   in SPT that is No_access and V_bit off\n");
	   else
		writes("   in P1PT that is No_access and V_bit off\n");
	ac_error1();
	asm("halt");
	
asm("vp_retpc:");
	*scb_base0 = saved_vec1;		/* Restore original vector */
	*scb_base1 = saved_vec2;
	access_md = saved_pte  & 0xf8000000;	/* Restore test PTE in SPT */
	pfn = saved_pte & 0x3fffff;
	fixpfn_pte(SBR,test_pte,&saved_pte,pfn); 
	fixpv_pte(SBR,test_pte,&saved_pte,access_md); 

	if (tflag==0)
		chk_fpars("");
}




ptf_handler()
{
asm(".align 2");
/* 	Handler of protection fault exception.      */
asm("prot_flt4:");
	asm("movab _act_par0,_p_ptr");	/* Set pointer to fault parameters */
	asm("movl  (sp)+,_act_par0");
	asm("movl  (sp)+,_act_par1");
	asm("movl  (sp)+,_act_par2");
	asm("movl  (sp)+,_act_par3");

	/* return to test */
	if (trans_excpt==0)
		asm("jmp  vp_retpc");
	     else
		asm("jmp  at_flt");		
		
asm(".align 2");
/* 	Handler of translation not valid fault.      */
asm("trans_flt4:");
	trans_excpt++;			/* Set flag */
	asm("jmp  prot_flt4");		
}



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