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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman|
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1.1 ! root 1: LL0: ! 2: .data ! 3: .set SBR,0 ! 4: .set SLR,1 ! 5: .set P0BR,2 ! 6: .set P0LR,3 ! 7: .set P1BR,4 ! 8: .set P1LR,5 ! 9: .set P2BR,6 ! 10: .set P2LR,7 ! 11: .set IPL,8 ! 12: .set MAPEN,9 ! 13: .set MME,9 ! 14: .set TBIA,10 ! 15: .set TBIS,11 ! 16: .set DCK,12 ! 17: .set CCK,13 ! 18: .set PCBB,14 ! 19: .set KSP,19 ! 20: .set USP,20 ! 21: .set CPMDCB,21 ! 22: .set PADC,25 ! 23: .set DCR,27 ! 24: .set DC_ON,1 ! 25: .set DC_OFF,2 ! 26: .set TB_ON,256 ! 27: .set TB_OFF,512 ! 28: .comm _trans_excpt,4 ! 29: .text ! 30: .align 1 ! 31: .globl _pv_test ! 32: _pv_test: ! 33: .word L40 ! 34: # ! 35: # #include "definitions" ! 36: # ! 37: # ! 38: # extern long iob0, iob1, iob2, iob3, ss1; ! 39: # extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7; ! 40: # extern long *p_ptr, ret_adr, exp_par0, exp_par1, exp_par2, exp_par3; ! 41: # extern long act_par0, act_par1, act_par2, act_par3, saved_psl; ! 42: # extern long Failpc, Tpsl , test_va; ! 43: # ! 44: # /* The purpose of this test is to validate that TAHOE will check access ! 45: # protection bits before checking the valid of the PTE . ! 46: # This test run in user P0 space ,KERNEL privilege and try to access ! 47: # system and P1 space which have corresponding PTE set as : ! 48: # Protection bits : Kernel read only ! 49: # Valid bit : Off ! 50: # */ ! 51: # ! 52: # ! 53: # long trans_excpt; ! 54: # ! 55: # pv_test() ! 56: # { long *pt_ptr; ! 57: jbr L42 ! 58: L43: ! 59: # ! 60: # if (ss1) ! 61: tstl _ss1 ! 62: jeql L44 ! 63: # writes("** Subtest5 : order of memory management exceptions\n"); ! 64: .data 1 ! 65: L46: ! 66: .ascii "** Subtest5 : order of memory management exceptions\12\0" ! 67: .text ! 68: pushl $L46 ! 69: callf $8,_writes ! 70: # pt_ptr = (long *)0; ! 71: L44: ! 72: clrl -56(fp) ! 73: # asm("mfpr $SBR,_savvec4"); ! 74: mfpr $SBR,_savvec4 ! 75: # savvec4 |= 0xc0000000; /* Make it system virtual address */ ! 76: orl2 $-1073741824,_savvec4 ! 77: # asm("mtpr _savvec4,$P0BR"); ! 78: mtpr _savvec4,$P0BR ! 79: # asm("mfpr $SLR,_savvec4"); ! 80: mfpr $SLR,_savvec4 ! 81: # asm("mtpr _savvec4,$P0LR"); ! 82: mtpr _savvec4,$P0LR ! 83: # ! 84: # asm("mtpr $4,$DCK"); ! 85: mtpr $4,$DCK ! 86: # asm("mtpr $0,$TBIA"); ! 87: mtpr $0,$TBIA ! 88: # asm("mtpr $0,$PADC"); ! 89: mtpr $0,$PADC ! 90: # asm("mtpr $1,$MME"); /* Enable MME */ ! 91: mtpr $1,$MME ! 92: # asm("jmp *$0f"); /* Go virtual .. */ ! 93: jmp *$0f ! 94: # asm("0:"); ! 95: 0: ! 96: # ! 97: # vp_tst(IOB0, SBR, SADDR); ! 98: pushl $-1073741824 ! 99: pushl $0 ! 100: andl3 $1073740800,$_iob0,r0 ! 101: shrl $10,r0,r0 ! 102: andl2 $1048575,r0 ! 103: pushl r0 ! 104: callf $16,_vp_tst ! 105: # ! 106: # /* Set up P1PT */ ! 107: # pt_ptr = &u0p1pt; ! 108: movl $_u0p1pt,-56(fp) ! 109: # *pt_ptr = IOB1; /* 1st PTE of P1 mapped to IOB1 */ ! 110: andl3 $1073740800,$_iob1,r0 ! 111: shrl $10,r0,r0 ! 112: andl2 $1048575,r0 ! 113: movl r0,*-56(fp) ! 114: # savvec4 = ((long)pt_ptr) | SADDR; ! 115: orl3 $-1073741824,-56(fp),r0 ! 116: movl r0,_savvec4 ! 117: # asm("mtpr _savvec4,$P1BR"); ! 118: mtpr _savvec4,$P1BR ! 119: # asm("mtpr $1,$P1LR"); ! 120: mtpr $1,$P1LR ! 121: # vp_tst(TEST_PTEP1, P1BR, P1ADDR); ! 122: pushl $1073741824 ! 123: pushl $4 ! 124: pushl $0 ! 125: callf $16,_vp_tst ! 126: # ! 127: # asm("mtpr $0,$MME"); /* Back to physical */ ! 128: mtpr $0,$MME ! 129: # asm("mtpr $0,$P0LR"); /* Invalidate P0 space */ ! 130: mtpr $0,$P0LR ! 131: # } ! 132: ret ! 133: .set L40,0x0 ! 134: L42: ! 135: subl3 $56,fp,sp ! 136: jbr L43 ! 137: .data ! 138: .text ! 139: .align 1 ! 140: .globl _vp_tst ! 141: _vp_tst: ! 142: .word L48 ! 143: # ! 144: # ! 145: # vp_tst(test_pte, pg_tbl, space) ! 146: # long test_pte, pg_tbl, space; ! 147: # { ! 148: jbr L50 ! 149: L51: ! 150: # long lgword, pfn, saved_vec1, saved_pte, test_adr, access_md; ! 151: # long *scb_base0, *scb_base1, saved_vec2, tflag; ! 152: # char *msg1, *msg2; ! 153: # ! 154: # trans_excpt = tflag = 0; ! 155: clrl -92(fp) ! 156: movl -92(fp),_trans_excpt ! 157: # /* Set v and protection bits of target PTE in SPT */ ! 158: # access_md = PTE_NOACC; ! 159: clrl -76(fp) ! 160: # fixpv_pte(pg_tbl,test_pte,&saved_pte,access_md); ! 161: pushl -76(fp) ! 162: subl3 $68,fp,r0 ! 163: pushl r0 ! 164: pushl 4(fp) ! 165: pushl 8(fp) ! 166: callf $20,_fixpv_pte ! 167: # ! 168: # /* Set expected parameter words */ ! 169: # exp_par0 = 4; /* protection violation, write access */ ! 170: movl $4,_exp_par0 ! 171: # test_adr = ( (test_pte) << PGSHIFT) | space; ! 172: shll $10,4(fp),r0 ! 173: orl2 12(fp),r0 ! 174: movl r0,-72(fp) ! 175: # test_va = exp_par1 = test_adr; ! 176: movl -72(fp),_exp_par1 ! 177: movl _exp_par1,r0 ! 178: movl r0,_test_va ! 179: # asm("movab sys_wr,_exp_par2"); /* PC at faulting instruction */ ! 180: movab sys_wr,_exp_par2 ! 181: # Failpc = exp_par2; ! 182: movl _exp_par2,_Failpc ! 183: # exp_par3 = 0; ! 184: clrl _exp_par3 ! 185: # ! 186: # /* Set handler of protection fault */ ! 187: # scb_base0 = scb_base1 = &scb; ! 188: movl $_scb,-84(fp) ! 189: movl -84(fp),-80(fp) ! 190: # scb_base0 += PROT_VEC; ! 191: addl2 $188,-80(fp) ! 192: # saved_vec1 = *scb_base0; /* Save original vector */ ! 193: movl *-80(fp),-64(fp) ! 194: # asm("movab prot_flt4,_savvec4"); ! 195: movab prot_flt4,_savvec4 ! 196: # *scb_base0 = savvec4; /* Set new vector */ ! 197: movl _savvec4,*-80(fp) ! 198: # ! 199: # /* Set handler of translation fault */ ! 200: # scb_base1 += TRANS_VEC; ! 201: addl2 $192,-84(fp) ! 202: # saved_vec2 = *scb_base1; /* Save original vector */ ! 203: movl *-84(fp),-88(fp) ! 204: # asm("movab trans_flt4,_savvec4"); ! 205: movab trans_flt4,_savvec4 ! 206: # *scb_base1 = savvec4; /* Set new vector */ ! 207: movl _savvec4,*-84(fp) ! 208: # ! 209: # asm("movpsl _exp_par3"); /* Set expected PSL */ ! 210: movpsl _exp_par3 ! 211: # exp_par3 &= 0xffffffc0; /* Mask out PSW flags */ ! 212: andl2 $-64,_exp_par3 ! 213: # Tpsl = exp_par3; ! 214: movl _exp_par3,_Tpsl ! 215: # asm("movl _exp_par1,r0"); ! 216: movl _exp_par1,r0 ! 217: # asm("sys_wr:"); ! 218: sys_wr: ! 219: # asm("movl $1,(r0)"); /* Should cause exception right here */ ! 220: movl $1,(r0) ! 221: # tflag++; ! 222: incl -92(fp) ! 223: # writes("** Expected protection fault did not occur when write\n"); ! 224: .data 1 ! 225: L53: ! 226: .ascii "** Expected protection fault did not occur when write\12\0" ! 227: .text ! 228: pushl $L53 ! 229: callf $8,_writes ! 230: # if (space==SADDR) ! 231: cmpl 12(fp),$-1073741824 ! 232: jneq L54 ! 233: # writes(" to a page in SPT that is No_access and V_bit off\n"); ! 234: .data 1 ! 235: L55: ! 236: .ascii " to a page in SPT that is No_access and V_bit off\12\0" ! 237: .text ! 238: pushl $L55 ! 239: callf $8,_writes ! 240: # else ! 241: jbr L56 ! 242: L54: ! 243: # writes(" to a page in P1PT that is No_access and V_bit off\n"); ! 244: .data 1 ! 245: L57: ! 246: .ascii " to a page in P1PT that is No_access and V_bit off\12\0" ! 247: .text ! 248: pushl $L57 ! 249: callf $8,_writes ! 250: L56: ! 251: # ac_error1(); ! 252: callf $4,_ac_error1 ! 253: # asm("halt"); ! 254: halt ! 255: # asm("jmp vp_retpc"); ! 256: jmp vp_retpc ! 257: # ! 258: # asm("at_flt:") ! 259: at_flt: ! 260: # tflag++; ! 261: incl -92(fp) ! 262: # writes("** Translation fault occured when write to a page \n"); ! 263: .data 1 ! 264: L59: ! 265: .ascii "** Translation fault occured when write to a page \12\0" ! 266: .text ! 267: pushl $L59 ! 268: callf $8,_writes ! 269: # if (space==SADDR) ! 270: cmpl 12(fp),$-1073741824 ! 271: jneq L60 ! 272: # writes(" in SPT that is No_access and V_bit off\n"); ! 273: .data 1 ! 274: L61: ! 275: .ascii " in SPT that is No_access and V_bit off\12\0" ! 276: .text ! 277: pushl $L61 ! 278: callf $8,_writes ! 279: # else ! 280: jbr L62 ! 281: L60: ! 282: # writes(" in P1PT that is No_access and V_bit off\n"); ! 283: .data 1 ! 284: L63: ! 285: .ascii " in P1PT that is No_access and V_bit off\12\0" ! 286: .text ! 287: pushl $L63 ! 288: callf $8,_writes ! 289: L62: ! 290: # ac_error1(); ! 291: callf $4,_ac_error1 ! 292: # asm("halt"); ! 293: halt ! 294: # ! 295: # asm("vp_retpc:"); ! 296: vp_retpc: ! 297: # *scb_base0 = saved_vec1; /* Restore original vector */ ! 298: movl -64(fp),*-80(fp) ! 299: # *scb_base1 = saved_vec2; ! 300: movl -88(fp),*-84(fp) ! 301: # access_md = saved_pte & 0xf8000000; /* Restore test PTE in SPT */ ! 302: andl3 $-134217728,-68(fp),r0 ! 303: movl r0,-76(fp) ! 304: # pfn = saved_pte & 0x3fffff; ! 305: andl3 $4194303,-68(fp),r0 ! 306: movl r0,-60(fp) ! 307: # fixpfn_pte(SBR,test_pte,&saved_pte,pfn); ! 308: pushl -60(fp) ! 309: subl3 $68,fp,r0 ! 310: pushl r0 ! 311: pushl 4(fp) ! 312: pushl $0 ! 313: callf $20,_fixpfn_pte ! 314: # fixpv_pte(SBR,test_pte,&saved_pte,access_md); ! 315: pushl -76(fp) ! 316: subl3 $68,fp,r0 ! 317: pushl r0 ! 318: pushl 4(fp) ! 319: pushl $0 ! 320: callf $20,_fixpv_pte ! 321: # ! 322: # if (tflag==0) ! 323: tstl -92(fp) ! 324: jneq L65 ! 325: # chk_fpars(""); ! 326: .data 1 ! 327: L67: ! 328: .ascii "\0" ! 329: .text ! 330: pushl $L67 ! 331: callf $8,_chk_fpars ! 332: # } ! 333: L65: ! 334: ret ! 335: .set L48,0x0 ! 336: L50: ! 337: subl3 $100,fp,sp ! 338: jbr L51 ! 339: .data ! 340: .text ! 341: .align 1 ! 342: .globl _ptf_handler ! 343: _ptf_handler: ! 344: .word L69 ! 345: # ! 346: # ! 347: # ! 348: # ! 349: # ptf_handler() ! 350: # { ! 351: jbr L71 ! 352: L72: ! 353: # asm(".align 2"); ! 354: .align 2 ! 355: # /* Handler of protection fault exception. */ ! 356: # asm("prot_flt4:"); ! 357: prot_flt4: ! 358: # asm("movab _act_par0,_p_ptr"); /* Set pointer to fault parameters */ ! 359: movab _act_par0,_p_ptr ! 360: # asm("movl (sp)+,_act_par0"); ! 361: movl (sp)+,_act_par0 ! 362: # asm("movl (sp)+,_act_par1"); ! 363: movl (sp)+,_act_par1 ! 364: # asm("movl (sp)+,_act_par2"); ! 365: movl (sp)+,_act_par2 ! 366: # asm("movl (sp)+,_act_par3"); ! 367: movl (sp)+,_act_par3 ! 368: # ! 369: # /* return to test */ ! 370: # if (trans_excpt==0) ! 371: tstl _trans_excpt ! 372: jneq L73 ! 373: # asm("jmp vp_retpc"); ! 374: jmp vp_retpc ! 375: # else ! 376: jbr L74 ! 377: L73: ! 378: # asm("jmp at_flt"); ! 379: jmp at_flt ! 380: L74: ! 381: # ! 382: # asm(".align 2"); ! 383: .align 2 ! 384: # /* Handler of translation not valid fault. */ ! 385: # asm("trans_flt4:"); ! 386: trans_flt4: ! 387: # trans_excpt++; /* Set flag */ ! 388: incl _trans_excpt ! 389: # asm("jmp prot_flt4"); ! 390: jmp prot_flt4 ! 391: # } ! 392: ret ! 393: .set L69,0x0 ! 394: L71: ! 395: jbr L72 ! 396: .data ! 397: # ! 398: #
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