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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman|
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Power 6/32 Unix version 1.2b
LL0:
.data
.set SBR,0
.set SLR,1
.set P0BR,2
.set P0LR,3
.set P1BR,4
.set P1LR,5
.set P2BR,6
.set P2LR,7
.set IPL,8
.set MAPEN,9
.set MME,9
.set TBIA,10
.set TBIS,11
.set DCK,12
.set CCK,13
.set PCBB,14
.set KSP,19
.set USP,20
.set CPMDCB,21
.set PADC,25
.set DCR,27
.set DC_ON,1
.set DC_OFF,2
.set TB_ON,256
.set TB_OFF,512
.comm _trans_excpt,4
.text
.align 1
.globl _pv_test
_pv_test:
.word L40
#
# #include "definitions"
#
#
# extern long iob0, iob1, iob2, iob3, ss1;
# extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7;
# extern long *p_ptr, ret_adr, exp_par0, exp_par1, exp_par2, exp_par3;
# extern long act_par0, act_par1, act_par2, act_par3, saved_psl;
# extern long Failpc, Tpsl , test_va;
#
# /* The purpose of this test is to validate that TAHOE will check access
# protection bits before checking the valid of the PTE .
# This test run in user P0 space ,KERNEL privilege and try to access
# system and P1 space which have corresponding PTE set as :
# Protection bits : Kernel read only
# Valid bit : Off
# */
#
#
# long trans_excpt;
#
# pv_test()
# { long *pt_ptr;
jbr L42
L43:
#
# if (ss1)
tstl _ss1
jeql L44
# writes("** Subtest5 : order of memory management exceptions\n");
.data 1
L46:
.ascii "** Subtest5 : order of memory management exceptions\12\0"
.text
pushl $L46
callf $8,_writes
# pt_ptr = (long *)0;
L44:
clrl -56(fp)
# asm("mfpr $SBR,_savvec4");
mfpr $SBR,_savvec4
# savvec4 |= 0xc0000000; /* Make it system virtual address */
orl2 $-1073741824,_savvec4
# asm("mtpr _savvec4,$P0BR");
mtpr _savvec4,$P0BR
# asm("mfpr $SLR,_savvec4");
mfpr $SLR,_savvec4
# asm("mtpr _savvec4,$P0LR");
mtpr _savvec4,$P0LR
#
# asm("mtpr $4,$DCK");
mtpr $4,$DCK
# asm("mtpr $0,$TBIA");
mtpr $0,$TBIA
# asm("mtpr $0,$PADC");
mtpr $0,$PADC
# asm("mtpr $1,$MME"); /* Enable MME */
mtpr $1,$MME
# asm("jmp *$0f"); /* Go virtual .. */
jmp *$0f
# asm("0:");
0:
#
# vp_tst(IOB0, SBR, SADDR);
pushl $-1073741824
pushl $0
andl3 $1073740800,$_iob0,r0
shrl $10,r0,r0
andl2 $1048575,r0
pushl r0
callf $16,_vp_tst
#
# /* Set up P1PT */
# pt_ptr = &u0p1pt;
movl $_u0p1pt,-56(fp)
# *pt_ptr = IOB1; /* 1st PTE of P1 mapped to IOB1 */
andl3 $1073740800,$_iob1,r0
shrl $10,r0,r0
andl2 $1048575,r0
movl r0,*-56(fp)
# savvec4 = ((long)pt_ptr) | SADDR;
orl3 $-1073741824,-56(fp),r0
movl r0,_savvec4
# asm("mtpr _savvec4,$P1BR");
mtpr _savvec4,$P1BR
# asm("mtpr $1,$P1LR");
mtpr $1,$P1LR
# vp_tst(TEST_PTEP1, P1BR, P1ADDR);
pushl $1073741824
pushl $4
pushl $0
callf $16,_vp_tst
#
# asm("mtpr $0,$MME"); /* Back to physical */
mtpr $0,$MME
# asm("mtpr $0,$P0LR"); /* Invalidate P0 space */
mtpr $0,$P0LR
# }
ret
.set L40,0x0
L42:
subl3 $56,fp,sp
jbr L43
.data
.text
.align 1
.globl _vp_tst
_vp_tst:
.word L48
#
#
# vp_tst(test_pte, pg_tbl, space)
# long test_pte, pg_tbl, space;
# {
jbr L50
L51:
# long lgword, pfn, saved_vec1, saved_pte, test_adr, access_md;
# long *scb_base0, *scb_base1, saved_vec2, tflag;
# char *msg1, *msg2;
#
# trans_excpt = tflag = 0;
clrl -92(fp)
movl -92(fp),_trans_excpt
# /* Set v and protection bits of target PTE in SPT */
# access_md = PTE_NOACC;
clrl -76(fp)
# fixpv_pte(pg_tbl,test_pte,&saved_pte,access_md);
pushl -76(fp)
subl3 $68,fp,r0
pushl r0
pushl 4(fp)
pushl 8(fp)
callf $20,_fixpv_pte
#
# /* Set expected parameter words */
# exp_par0 = 4; /* protection violation, write access */
movl $4,_exp_par0
# test_adr = ( (test_pte) << PGSHIFT) | space;
shll $10,4(fp),r0
orl2 12(fp),r0
movl r0,-72(fp)
# test_va = exp_par1 = test_adr;
movl -72(fp),_exp_par1
movl _exp_par1,r0
movl r0,_test_va
# asm("movab sys_wr,_exp_par2"); /* PC at faulting instruction */
movab sys_wr,_exp_par2
# Failpc = exp_par2;
movl _exp_par2,_Failpc
# exp_par3 = 0;
clrl _exp_par3
#
# /* Set handler of protection fault */
# scb_base0 = scb_base1 = &scb;
movl $_scb,-84(fp)
movl -84(fp),-80(fp)
# scb_base0 += PROT_VEC;
addl2 $188,-80(fp)
# saved_vec1 = *scb_base0; /* Save original vector */
movl *-80(fp),-64(fp)
# asm("movab prot_flt4,_savvec4");
movab prot_flt4,_savvec4
# *scb_base0 = savvec4; /* Set new vector */
movl _savvec4,*-80(fp)
#
# /* Set handler of translation fault */
# scb_base1 += TRANS_VEC;
addl2 $192,-84(fp)
# saved_vec2 = *scb_base1; /* Save original vector */
movl *-84(fp),-88(fp)
# asm("movab trans_flt4,_savvec4");
movab trans_flt4,_savvec4
# *scb_base1 = savvec4; /* Set new vector */
movl _savvec4,*-84(fp)
#
# asm("movpsl _exp_par3"); /* Set expected PSL */
movpsl _exp_par3
# exp_par3 &= 0xffffffc0; /* Mask out PSW flags */
andl2 $-64,_exp_par3
# Tpsl = exp_par3;
movl _exp_par3,_Tpsl
# asm("movl _exp_par1,r0");
movl _exp_par1,r0
# asm("sys_wr:");
sys_wr:
# asm("movl $1,(r0)"); /* Should cause exception right here */
movl $1,(r0)
# tflag++;
incl -92(fp)
# writes("** Expected protection fault did not occur when write\n");
.data 1
L53:
.ascii "** Expected protection fault did not occur when write\12\0"
.text
pushl $L53
callf $8,_writes
# if (space==SADDR)
cmpl 12(fp),$-1073741824
jneq L54
# writes(" to a page in SPT that is No_access and V_bit off\n");
.data 1
L55:
.ascii " to a page in SPT that is No_access and V_bit off\12\0"
.text
pushl $L55
callf $8,_writes
# else
jbr L56
L54:
# writes(" to a page in P1PT that is No_access and V_bit off\n");
.data 1
L57:
.ascii " to a page in P1PT that is No_access and V_bit off\12\0"
.text
pushl $L57
callf $8,_writes
L56:
# ac_error1();
callf $4,_ac_error1
# asm("halt");
halt
# asm("jmp vp_retpc");
jmp vp_retpc
#
# asm("at_flt:")
at_flt:
# tflag++;
incl -92(fp)
# writes("** Translation fault occured when write to a page \n");
.data 1
L59:
.ascii "** Translation fault occured when write to a page \12\0"
.text
pushl $L59
callf $8,_writes
# if (space==SADDR)
cmpl 12(fp),$-1073741824
jneq L60
# writes(" in SPT that is No_access and V_bit off\n");
.data 1
L61:
.ascii " in SPT that is No_access and V_bit off\12\0"
.text
pushl $L61
callf $8,_writes
# else
jbr L62
L60:
# writes(" in P1PT that is No_access and V_bit off\n");
.data 1
L63:
.ascii " in P1PT that is No_access and V_bit off\12\0"
.text
pushl $L63
callf $8,_writes
L62:
# ac_error1();
callf $4,_ac_error1
# asm("halt");
halt
#
# asm("vp_retpc:");
vp_retpc:
# *scb_base0 = saved_vec1; /* Restore original vector */
movl -64(fp),*-80(fp)
# *scb_base1 = saved_vec2;
movl -88(fp),*-84(fp)
# access_md = saved_pte & 0xf8000000; /* Restore test PTE in SPT */
andl3 $-134217728,-68(fp),r0
movl r0,-76(fp)
# pfn = saved_pte & 0x3fffff;
andl3 $4194303,-68(fp),r0
movl r0,-60(fp)
# fixpfn_pte(SBR,test_pte,&saved_pte,pfn);
pushl -60(fp)
subl3 $68,fp,r0
pushl r0
pushl 4(fp)
pushl $0
callf $20,_fixpfn_pte
# fixpv_pte(SBR,test_pte,&saved_pte,access_md);
pushl -76(fp)
subl3 $68,fp,r0
pushl r0
pushl 4(fp)
pushl $0
callf $20,_fixpv_pte
#
# if (tflag==0)
tstl -92(fp)
jneq L65
# chk_fpars("");
.data 1
L67:
.ascii "\0"
.text
pushl $L67
callf $8,_chk_fpars
# }
L65:
ret
.set L48,0x0
L50:
subl3 $100,fp,sp
jbr L51
.data
.text
.align 1
.globl _ptf_handler
_ptf_handler:
.word L69
#
#
#
#
# ptf_handler()
# {
jbr L71
L72:
# asm(".align 2");
.align 2
# /* Handler of protection fault exception. */
# asm("prot_flt4:");
prot_flt4:
# asm("movab _act_par0,_p_ptr"); /* Set pointer to fault parameters */
movab _act_par0,_p_ptr
# asm("movl (sp)+,_act_par0");
movl (sp)+,_act_par0
# asm("movl (sp)+,_act_par1");
movl (sp)+,_act_par1
# asm("movl (sp)+,_act_par2");
movl (sp)+,_act_par2
# asm("movl (sp)+,_act_par3");
movl (sp)+,_act_par3
#
# /* return to test */
# if (trans_excpt==0)
tstl _trans_excpt
jneq L73
# asm("jmp vp_retpc");
jmp vp_retpc
# else
jbr L74
L73:
# asm("jmp at_flt");
jmp at_flt
L74:
#
# asm(".align 2");
.align 2
# /* Handler of translation not valid fault. */
# asm("trans_flt4:");
trans_flt4:
# trans_excpt++; /* Set flag */
incl _trans_excpt
# asm("jmp prot_flt4");
jmp prot_flt4
# }
ret
.set L69,0x0
L71:
jbr L72
.data
#
#
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