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Annotation of cci/d/memman/ucbit.c, revision 1.1

1.1     ! root        1: 
        !             2: #include "definitions"
        !             3: 
        !             4: extern long ss1, savvec4, savvec5, savvec7, u0p1pt, iob2;
        !             5: extern long Tpsl, Failpc, test_va;
        !             6: 
        !             7: /*  This test check the Uncachable bit in PTE of P1PT */
        !             8: 
        !             9: ucbit_chk()
        !            10: {      long *temp;
        !            11: 
        !            12:        if (ss1) writes("** Subtest6 : PTE non_cachable bit test\n");
        !            13:        return(0);
        !            14:        temp = (long *)0;
        !            15:        asm("mfpr $SBR,_savvec4");
        !            16:        savvec4 |= 0xc0000000;
        !            17:        asm("mtpr _savvec4,$P0BR");     /* Double map P0 into System space */
        !            18:        asm("mtpr _savvec4,$P1BR");     /* Double map P1 into System space */
        !            19:        asm("mfpr $SLR,_savvec4");
        !            20:        asm("mtpr _savvec4,$P0LR");
        !            21:        asm("mtpr _savvec4,$P1LR");
        !            22: 
        !            23:        asm("mtpr $3,$DCK");
        !            24:        asm("mtpr $0,$TBIA");
        !            25:        asm("mtpr $0,$PADC");
        !            26:        asm("mtpr $1,$MME");
        !            27:        asm("jmp  *$0f");               /* Go virtual */
        !            28: asm("0:");
        !            29:        asm("mtpr $TB_OFF,$DCR");       /* Turn off Translation buffer */
        !            30:        pte_nc(IOB2);
        !            31:        asm("mtpr $TB_ON,$DCR");        /* Turn on Translation buffer */
        !            32:        asm("mtpr $0,$MME");
        !            33:        asm("mtpr $0,$P0LR");
        !            34:        asm("mtpr $0,$P1LR");
        !            35: 
        !            36: }
        !            37: 
        !            38: asm(".set TDCK,0x658");                /* Addr of DCK in processor storage area */
        !            39: asm(".set P1DC,24");
        !            40: 
        !            41: pte_nc(pte_no)
        !            42: long pte_no;
        !            43: {
        !            44:        long old_pte;
        !            45:        register long *vaddr, aval, pte1, *pte_adr, paddr, eval;
        !            46:        /* vaddr = R12; aval = R11; pte1 = R10; pte_adr = R9; paddr = R8 */
        !            47: 
        !            48:        eval = 0xabbaabba;              /* Test pattern */
        !            49:        asm("mfpr $P1BR,_savvec7");
        !            50:        pte_adr = (long *)savvec7;
        !            51:        pte_adr += pte_no;              /* Address of PTE used in test */
        !            52:        asm("movpsl _Tpsl");
        !            53: 
        !            54:        vaddr = (long *)((pte_no<<PGSHIFT) | P1ADDR);   /* VA of test loc */
        !            55:        test_va = (long)vaddr;
        !            56:        paddr = ((long)vaddr) & 0x3fffffff;             /* PA of test loc */
        !            57:        *vaddr = eval;          /* Write pattern to test loc,also go in cache */
        !            58:        fixmuc_pte(P1BR,pte_no,&old_pte,0);     /* Set PTE_N bit to 0 */
        !            59:        pte1 = old_pte | 0x01000000;            /* Set PTE_N bit to 1 */
        !            60: 
        !            61:        asm("movl $0,*$TDCK");          /* Set DCK in PSA to 0  */
        !            62:        asm("mtpr $0,$MME");            /* Disable MME */
        !            63:        asm("mtpr r8,$P1DC");           /* Purge test loc. in data cache */
        !            64:                                        /* Using PA, Now DCK should be 0  */    
        !            65:        asm("mtpr $1,$MME");            /* Enable MME again */
        !            66:        asm("mtpr $DC_ON,$DCR");        /* Enable data cache */
        !            67: asm("Uc0:");
        !            68:        aval = *vaddr;                  /* Read test loc, should get a hit ! */
        !            69:        if (aval == eval)
        !            70:                {
        !            71:                asm("mtpr $3,$DCK");
        !            72:                asm("movab Uc0,_Failpc");
        !            73:                writes("** fail to get a cache hit\n");
        !            74:                ac_error1();
        !            75:                writes("** PTE : "); writeh(old_pte);
        !            76:                writes("\n** Expected value (purge pattern) : ");writeh(0);
        !            77:                writes("\n** Actual value   : ");writeh(aval);writec('\n');
        !            78:                asm("halt");
        !            79:                }
        !            80:        aval = aval;                    /* Dummy !! */
        !            81:        asm("movl r10,(r9)");           /* Write PTE with PTE_N == 1 back */
        !            82: asm("Uc1:");
        !            83:        aval = *vaddr;                  /* Read back ,should be from memory */
        !            84:        asm("mtpr $3,$DCK");
        !            85:        asm("mtpr $DC_OFF,$DCR");       /* Disable data cache */
        !            86:        if (aval != eval)               /* check result */
        !            87:                {               /* ERROR */
        !            88:               writes("** Page is cached even the PTE uncachable bit is set\n");
        !            89:                asm("movab Uc1,_Failpc");
        !            90:                ac_error1();
        !            91:                writes("** PTE : "); writeh(pte1); writec('\n');
        !            92:                writes("** Expected value : ");writeh(eval);writec('\n');
        !            93:                writes("** Actual value   : ");writeh(aval);writec('\n');
        !            94:                asm("halt");
        !            95:                }
        !            96: }
        !            97: 

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