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Power 6/32 Unix version 1.2b

#include "definitions"

extern long ss1, savvec4, savvec5, savvec7, u0p1pt, iob2;
extern long Tpsl, Failpc, test_va;

/*  This test check the Uncachable bit in PTE of P1PT */

ucbit_chk()
{	long *temp;

	if (ss1) writes("** Subtest6 : PTE non_cachable bit test\n");
	return(0);
	temp = (long *)0;
	asm("mfpr $SBR,_savvec4");
	savvec4 |= 0xc0000000;
	asm("mtpr _savvec4,$P0BR");	/* Double map P0 into System space */
	asm("mtpr _savvec4,$P1BR");	/* Double map P1 into System space */
	asm("mfpr $SLR,_savvec4");
	asm("mtpr _savvec4,$P0LR");
	asm("mtpr _savvec4,$P1LR");

	asm("mtpr $3,$DCK");
	asm("mtpr $0,$TBIA");
	asm("mtpr $0,$PADC");
	asm("mtpr $1,$MME");
	asm("jmp  *$0f");		/* Go virtual */
asm("0:");
	asm("mtpr $TB_OFF,$DCR");	/* Turn off Translation buffer */
	pte_nc(IOB2);
	asm("mtpr $TB_ON,$DCR");	/* Turn on Translation buffer */
	asm("mtpr $0,$MME");
	asm("mtpr $0,$P0LR");
	asm("mtpr $0,$P1LR");

}

asm(".set TDCK,0x658");		/* Addr of DCK in processor storage area */
asm(".set P1DC,24");

pte_nc(pte_no)
long pte_no;
{
	long old_pte;
	register long *vaddr, aval, pte1, *pte_adr, paddr, eval;
	/* vaddr = R12; aval = R11; pte1 = R10; pte_adr = R9; paddr = R8 */

	eval = 0xabbaabba;		/* Test pattern */
	asm("mfpr $P1BR,_savvec7");
	pte_adr = (long *)savvec7;
	pte_adr += pte_no;		/* Address of PTE used in test */
	asm("movpsl _Tpsl");

	vaddr = (long *)((pte_no<<PGSHIFT) | P1ADDR);	/* VA of test loc */
	test_va = (long)vaddr;
	paddr = ((long)vaddr) & 0x3fffffff;		/* PA of test loc */
	*vaddr = eval;		/* Write pattern to test loc,also go in cache */
	fixmuc_pte(P1BR,pte_no,&old_pte,0);	/* Set PTE_N bit to 0 */
	pte1 = old_pte | 0x01000000;		/* Set PTE_N bit to 1 */

	asm("movl $0,*$TDCK");		/* Set DCK in PSA to 0	*/
	asm("mtpr $0,$MME");		/* Disable MME */
	asm("mtpr r8,$P1DC");		/* Purge test loc. in data cache */
					/* Using PA, Now DCK should be 0  */	
	asm("mtpr $1,$MME");		/* Enable MME again */
	asm("mtpr $DC_ON,$DCR");	/* Enable data cache */
asm("Uc0:");
	aval = *vaddr;			/* Read test loc, should get a hit ! */
	if (aval == eval)
		{
		asm("mtpr $3,$DCK");
		asm("movab Uc0,_Failpc");
		writes("** fail to get a cache hit\n");
		ac_error1();
		writes("** PTE : "); writeh(old_pte);
		writes("\n** Expected value (purge pattern) : ");writeh(0);
		writes("\n** Actual value   : ");writeh(aval);writec('\n');
		asm("halt");
		}
	aval = aval;			/* Dummy !! */
	asm("movl r10,(r9)");		/* Write PTE with PTE_N == 1 back */
asm("Uc1:");
	aval = *vaddr;			/* Read back ,should be from memory */
	asm("mtpr $3,$DCK");
	asm("mtpr $DC_OFF,$DCR");	/* Disable data cache */
	if (aval != eval)		/* check result */
		{		/* ERROR */
	       writes("** Page is cached even the PTE uncachable bit is set\n");
		asm("movab Uc1,_Failpc");
		ac_error1();
		writes("** PTE : "); writeh(pte1); writec('\n');
		writes("** Expected value : ");writeh(eval);writec('\n');
		writes("** Actual value   : ");writeh(aval);writec('\n');
		asm("halt");
		}
}

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