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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman|
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1.1 root 1: LL0:
2: .data
3: .set SBR,0
4: .set SLR,1
5: .set P0BR,2
6: .set P0LR,3
7: .set P1BR,4
8: .set P1LR,5
9: .set P2BR,6
10: .set P2LR,7
11: .set IPL,8
12: .set MAPEN,9
13: .set MME,9
14: .set TBIA,10
15: .set TBIS,11
16: .set DCK,12
17: .set CCK,13
18: .set PCBB,14
19: .set KSP,19
20: .set USP,20
21: .set CPMDCB,21
22: .set PADC,25
23: .set DCR,27
24: .set DC_ON,1
25: .set DC_OFF,2
26: .set TB_ON,256
27: .set TB_OFF,512
28: .text
29: .align 1
30: .globl _ucbit_chk
31: _ucbit_chk:
32: .word L21
33: #
34: # #include "definitions"
35: #
36: # extern long ss1, savvec4, savvec5, savvec7, u0p1pt, iob2;
37: # extern long Tpsl, Failpc, test_va;
38: #
39: # /* This test check the Uncachable bit in PTE of P1PT */
40: #
41: # ucbit_chk()
42: # { long *temp;
43: jbr L23
44: L24:
45: #
46: # if (ss1) writes("** Subtest6 : PTE non_cachable bit test\n");
47: tstl _ss1
48: jeql L25
49: .data 1
50: L27:
51: .ascii "** Subtest6 : PTE non_cachable bit test\12\0"
52: .text
53: pushl $L27
54: callf $8,_writes
55: # temp = (long *)0;
56: L25:
57: clrl -56(fp)
58: # asm("mfpr $SBR,_savvec4");
59: mfpr $SBR,_savvec4
60: # savvec4 |= 0xc0000000;
61: orl2 $-1073741824,_savvec4
62: # asm("mtpr _savvec4,$P0BR"); /* Double map P0 into System space */
63: mtpr _savvec4,$P0BR
64: # asm("mtpr _savvec4,$P1BR"); /* Double map P1 into System space */
65: mtpr _savvec4,$P1BR
66: # asm("mfpr $SLR,_savvec4");
67: mfpr $SLR,_savvec4
68: # asm("mtpr _savvec4,$P0LR");
69: mtpr _savvec4,$P0LR
70: # asm("mtpr _savvec4,$P1LR");
71: mtpr _savvec4,$P1LR
72: #
73: # asm("mtpr $3,$DCK");
74: mtpr $3,$DCK
75: # asm("mtpr $0,$TBIA");
76: mtpr $0,$TBIA
77: # asm("mtpr $0,$PADC");
78: mtpr $0,$PADC
79: # asm("mtpr $1,$MME");
80: mtpr $1,$MME
81: # asm("jmp *$0f"); /* Go virtual */
82: jmp *$0f
83: # asm("0:");
84: 0:
85: # asm("mtpr $TB_OFF,$DCR"); /* Turn off Translation buffer */
86: mtpr $TB_OFF,$DCR
87: # pte_nc(IOB2);
88: andl3 $1073740800,$_iob2,r0
89: shrl $10,r0,r0
90: andl2 $1048575,r0
91: pushl r0
92: callf $8,_pte_nc
93: # asm("mtpr $TB_ON,$DCR"); /* Turn on Translation buffer */
94: mtpr $TB_ON,$DCR
95: # asm("mtpr $0,$MME");
96: mtpr $0,$MME
97: # asm("mtpr $0,$P0LR");
98: mtpr $0,$P0LR
99: # asm("mtpr $0,$P1LR");
100: mtpr $0,$P1LR
101: #
102: # }
103: ret
104: .set L21,0x0
105: L23:
106: subl3 $56,fp,sp
107: jbr L24
108: .data
109: .set TDCK,0x658
110: .set P1DC,24
111: .text
112: .align 1
113: .globl _pte_nc
114: _pte_nc:
115: .word L29
116: #
117: # asm(".set TDCK,0x658"); /* Addr of DCK in processor storage area */
118: # asm(".set P1DC,24");
119: #
120: # pte_nc(pte_no)
121: # long pte_no;
122: # {
123: jbr L31
124: L32:
125: # long old_pte;
126: # register long *vaddr, aval, pte1, *pte_adr, paddr, eval;
127: # /* vaddr = R12; aval = R11; pte1 = R10; pte_adr = R9; paddr = R8 */
128: #
129: # eval = 0xabbaabba; /* Test pattern */
130: movl $-1413829702,r7
131: # asm("mfpr $P1BR,_savvec7");
132: mfpr $P1BR,_savvec7
133: # pte_adr = (long *)savvec7;
134: movl _savvec7,r9
135: # pte_adr += pte_no; /* Address of PTE used in test */
136: shll $2,4(fp),r0
137: addl2 r0,r9
138: # asm("movpsl _Tpsl");
139: movpsl _Tpsl
140: #
141: # vaddr = (long *)((pte_no<<PGSHIFT) | P1ADDR); /* VA of test loc */
142: shll $10,4(fp),r0
143: orl2 $1073741824,r0
144: movl r0,r12
145: # test_va = (long)vaddr;
146: movl r12,_test_va
147: # paddr = ((long)vaddr) & 0x3fffffff; /* PA of test loc */
148: andl3 $1073741823,r12,r0
149: movl r0,r8
150: # *vaddr = eval; /* Write pattern to test loc,also go in cache */
151: movl r7,(r12)
152: # fixmuc_pte(P1BR,pte_no,&old_pte,0); /* Set PTE_N bit to 0 */
153: pushl $0
154: subl3 $56,fp,r0
155: pushl r0
156: pushl 4(fp)
157: pushl $4
158: callf $20,_fixmuc_pte
159: # pte1 = old_pte | 0x01000000; /* Set PTE_N bit to 1 */
160: orl3 $16777216,-56(fp),r0
161: movl r0,r10
162: #
163: # asm("movl $0,*$TDCK"); /* Set DCK in PSA to 0 */
164: movl $0,*$TDCK
165: # asm("mtpr $0,$MME"); /* Disable MME */
166: mtpr $0,$MME
167: # asm("mtpr r8,$P1DC"); /* Purge test loc. in data cache */
168: mtpr r8,$P1DC
169: # /* Using PA, Now DCK should be 0 */
170: # asm("mtpr $1,$MME"); /* Enable MME again */
171: mtpr $1,$MME
172: # asm("mtpr $DC_ON,$DCR"); /* Enable data cache */
173: mtpr $DC_ON,$DCR
174: # asm("Uc0:");
175: Uc0:
176: # aval = *vaddr; /* Read test loc, should get a hit ! */
177: movl (r12),r11
178: # if (aval == eval)
179: cmpl r11,r7
180: jneq L34
181: # {
182: # asm("mtpr $3,$DCK");
183: mtpr $3,$DCK
184: # asm("movab Uc0,_Failpc");
185: movab Uc0,_Failpc
186: # writes("** fail to get a cache hit\n");
187: .data 1
188: L35:
189: .ascii "** fail to get a cache hit\12\0"
190: .text
191: pushl $L35
192: callf $8,_writes
193: # ac_error1();
194: callf $4,_ac_error1
195: # writes("** PTE : "); writeh(old_pte);
196: .data 1
197: L37:
198: .ascii "** PTE : \0"
199: .text
200: pushl $L37
201: callf $8,_writes
202: pushl -56(fp)
203: callf $8,_writeh
204: # writes("\n** Expected value (purge pattern) : ");writeh(0);
205: .data 1
206: L39:
207: .ascii "\12** Expected value (purge pattern) : \0"
208: .text
209: pushl $L39
210: callf $8,_writes
211: pushl $0
212: callf $8,_writeh
213: # writes("\n** Actual value : ");writeh(aval);writec('\n');
214: .data 1
215: L40:
216: .ascii "\12** Actual value : \0"
217: .text
218: pushl $L40
219: callf $8,_writes
220: pushl r11
221: callf $8,_writeh
222: pushl $10
223: callf $8,_writec
224: # asm("halt");
225: halt
226: # }
227: # aval = aval; /* Dummy !! */
228: L34:
229: movl r11,r11
230: # asm("movl r10,(r9)"); /* Write PTE with PTE_N == 1 back */
231: movl r10,(r9)
232: # asm("Uc1:");
233: Uc1:
234: # aval = *vaddr; /* Read back ,should be from memory */
235: movl (r12),r11
236: # asm("mtpr $3,$DCK");
237: mtpr $3,$DCK
238: # asm("mtpr $DC_OFF,$DCR"); /* Disable data cache */
239: mtpr $DC_OFF,$DCR
240: # if (aval != eval) /* check result */
241: cmpl r11,r7
242: jeql L42
243: # { /* ERROR */
244: # writes("** Page is cached even the PTE uncachable bit is set\n");
245: .data 1
246: L43:
247: .ascii "** Page is cached even the PTE uncachable bit is set\12\0"
248: .text
249: pushl $L43
250: callf $8,_writes
251: # asm("movab Uc1,_Failpc");
252: movab Uc1,_Failpc
253: # ac_error1();
254: callf $4,_ac_error1
255: # writes("** PTE : "); writeh(pte1); writec('\n');
256: .data 1
257: L44:
258: .ascii "** PTE : \0"
259: .text
260: pushl $L44
261: callf $8,_writes
262: pushl r10
263: callf $8,_writeh
264: pushl $10
265: callf $8,_writec
266: # writes("** Expected value : ");writeh(eval);writec('\n');
267: .data 1
268: L45:
269: .ascii "** Expected value : \0"
270: .text
271: pushl $L45
272: callf $8,_writes
273: pushl r7
274: callf $8,_writeh
275: pushl $10
276: callf $8,_writec
277: # writes("** Actual value : ");writeh(aval);writec('\n');
278: .data 1
279: L46:
280: .ascii "** Actual value : \0"
281: .text
282: pushl $L46
283: callf $8,_writes
284: pushl r11
285: callf $8,_writeh
286: pushl $10
287: callf $8,_writec
288: # asm("halt");
289: halt
290: # }
291: # }
292: L42:
293: ret
294: .set L29,0x1f80
295: L31:
296: subl3 $56,fp,sp
297: jbr L32
298: .data
299: #
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