cci/d/memman/ucbit.s - view

File: [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman / ucbit.s
Revision 1.1.1.1 (vendor branch): download - view: text, annotated - select for diffs
Sun Jul 28 12:24:19 2019 UTC (6 years, 11 months ago) by root
Branches: bsd, MAIN
CVS tags: v12b, v121, HEAD

Power 6/32 Unix version 1.2b

LL0: .data .set SBR,0 .set SLR,1 .set P0BR,2 .set P0LR,3 .set P1BR,4 .set P1LR,5 .set P2BR,6 .set P2LR,7 .set IPL,8 .set MAPEN,9 .set MME,9 .set TBIA,10 .set TBIS,11 .set DCK,12 .set CCK,13 .set PCBB,14 .set KSP,19 .set USP,20 .set CPMDCB,21 .set PADC,25 .set DCR,27 .set DC_ON,1 .set DC_OFF,2 .set TB_ON,256 .set TB_OFF,512 .text .align 1 .globl _ucbit_chk _ucbit_chk: .word L21 # # #include "definitions" # # extern long ss1, savvec4, savvec5, savvec7, u0p1pt, iob2; # extern long Tpsl, Failpc, test_va; # # /* This test check the Uncachable bit in PTE of P1PT */ # # ucbit_chk() # { long *temp; jbr L23 L24: # # if (ss1) writes("** Subtest6 : PTE non_cachable bit test\n"); tstl _ss1 jeql L25 .data 1 L27: .ascii "** Subtest6 : PTE non_cachable bit test\12\0" .text pushl $L27 callf $8,_writes # temp = (long *)0; L25: clrl -56(fp) # asm("mfpr $SBR,_savvec4"); mfpr $SBR,_savvec4 # savvec4 |= 0xc0000000; orl2 $-1073741824,_savvec4 # asm("mtpr _savvec4,$P0BR"); /* Double map P0 into System space */ mtpr _savvec4,$P0BR # asm("mtpr _savvec4,$P1BR"); /* Double map P1 into System space */ mtpr _savvec4,$P1BR # asm("mfpr $SLR,_savvec4"); mfpr $SLR,_savvec4 # asm("mtpr _savvec4,$P0LR"); mtpr _savvec4,$P0LR # asm("mtpr _savvec4,$P1LR"); mtpr _savvec4,$P1LR # # asm("mtpr $3,$DCK"); mtpr $3,$DCK # asm("mtpr $0,$TBIA"); mtpr $0,$TBIA # asm("mtpr $0,$PADC"); mtpr $0,$PADC # asm("mtpr $1,$MME"); mtpr $1,$MME # asm("jmp *$0f"); /* Go virtual */ jmp *$0f # asm("0:"); 0: # asm("mtpr $TB_OFF,$DCR"); /* Turn off Translation buffer */ mtpr $TB_OFF,$DCR # pte_nc(IOB2); andl3 $1073740800,$_iob2,r0 shrl $10,r0,r0 andl2 $1048575,r0 pushl r0 callf $8,_pte_nc # asm("mtpr $TB_ON,$DCR"); /* Turn on Translation buffer */ mtpr $TB_ON,$DCR # asm("mtpr $0,$MME"); mtpr $0,$MME # asm("mtpr $0,$P0LR"); mtpr $0,$P0LR # asm("mtpr $0,$P1LR"); mtpr $0,$P1LR # # } ret .set L21,0x0 L23: subl3 $56,fp,sp jbr L24 .data .set TDCK,0x658 .set P1DC,24 .text .align 1 .globl _pte_nc _pte_nc: .word L29 # # asm(".set TDCK,0x658"); /* Addr of DCK in processor storage area */ # asm(".set P1DC,24"); # # pte_nc(pte_no) # long pte_no; # { jbr L31 L32: # long old_pte; # register long *vaddr, aval, pte1, *pte_adr, paddr, eval; # /* vaddr = R12; aval = R11; pte1 = R10; pte_adr = R9; paddr = R8 */ # # eval = 0xabbaabba; /* Test pattern */ movl $-1413829702,r7 # asm("mfpr $P1BR,_savvec7"); mfpr $P1BR,_savvec7 # pte_adr = (long *)savvec7; movl _savvec7,r9 # pte_adr += pte_no; /* Address of PTE used in test */ shll $2,4(fp),r0 addl2 r0,r9 # asm("movpsl _Tpsl"); movpsl _Tpsl # # vaddr = (long *)((pte_no<<PGSHIFT) | P1ADDR); /* VA of test loc */ shll $10,4(fp),r0 orl2 $1073741824,r0 movl r0,r12 # test_va = (long)vaddr; movl r12,_test_va # paddr = ((long)vaddr) & 0x3fffffff; /* PA of test loc */ andl3 $1073741823,r12,r0 movl r0,r8 # *vaddr = eval; /* Write pattern to test loc,also go in cache */ movl r7,(r12) # fixmuc_pte(P1BR,pte_no,&old_pte,0); /* Set PTE_N bit to 0 */ pushl $0 subl3 $56,fp,r0 pushl r0 pushl 4(fp) pushl $4 callf $20,_fixmuc_pte # pte1 = old_pte | 0x01000000; /* Set PTE_N bit to 1 */ orl3 $16777216,-56(fp),r0 movl r0,r10 # # asm("movl $0,*$TDCK"); /* Set DCK in PSA to 0 */ movl $0,*$TDCK # asm("mtpr $0,$MME"); /* Disable MME */ mtpr $0,$MME # asm("mtpr r8,$P1DC"); /* Purge test loc. in data cache */ mtpr r8,$P1DC # /* Using PA, Now DCK should be 0 */ # asm("mtpr $1,$MME"); /* Enable MME again */ mtpr $1,$MME # asm("mtpr $DC_ON,$DCR"); /* Enable data cache */ mtpr $DC_ON,$DCR # asm("Uc0:"); Uc0: # aval = *vaddr; /* Read test loc, should get a hit ! */ movl (r12),r11 # if (aval == eval) cmpl r11,r7 jneq L34 # { # asm("mtpr $3,$DCK"); mtpr $3,$DCK # asm("movab Uc0,_Failpc"); movab Uc0,_Failpc # writes("** fail to get a cache hit\n"); .data 1 L35: .ascii "** fail to get a cache hit\12\0" .text pushl $L35 callf $8,_writes # ac_error1(); callf $4,_ac_error1 # writes("** PTE : "); writeh(old_pte); .data 1 L37: .ascii "** PTE : \0" .text pushl $L37 callf $8,_writes pushl -56(fp) callf $8,_writeh # writes("\n** Expected value (purge pattern) : ");writeh(0); .data 1 L39: .ascii "\12** Expected value (purge pattern) : \0" .text pushl $L39 callf $8,_writes pushl $0 callf $8,_writeh # writes("\n** Actual value : ");writeh(aval);writec('\n'); .data 1 L40: .ascii "\12** Actual value : \0" .text pushl $L40 callf $8,_writes pushl r11 callf $8,_writeh pushl $10 callf $8,_writec # asm("halt"); halt # } # aval = aval; /* Dummy !! */ L34: movl r11,r11 # asm("movl r10,(r9)"); /* Write PTE with PTE_N == 1 back */ movl r10,(r9) # asm("Uc1:"); Uc1: # aval = *vaddr; /* Read back ,should be from memory */ movl (r12),r11 # asm("mtpr $3,$DCK"); mtpr $3,$DCK # asm("mtpr $DC_OFF,$DCR"); /* Disable data cache */ mtpr $DC_OFF,$DCR # if (aval != eval) /* check result */ cmpl r11,r7 jeql L42 # { /* ERROR */ # writes("** Page is cached even the PTE uncachable bit is set\n"); .data 1 L43: .ascii "** Page is cached even the PTE uncachable bit is set\12\0" .text pushl $L43 callf $8,_writes # asm("movab Uc1,_Failpc"); movab Uc1,_Failpc # ac_error1(); callf $4,_ac_error1 # writes("** PTE : "); writeh(pte1); writec('\n'); .data 1 L44: .ascii "** PTE : \0" .text pushl $L44 callf $8,_writes pushl r10 callf $8,_writeh pushl $10 callf $8,_writec # writes("** Expected value : ");writeh(eval);writec('\n'); .data 1 L45: .ascii "** Expected value : \0" .text pushl $L45 callf $8,_writes pushl r7 callf $8,_writeh pushl $10 callf $8,_writec # writes("** Actual value : ");writeh(aval);writec('\n'); .data 1 L46: .ascii "** Actual value : \0" .text pushl $L46 callf $8,_writes pushl r11 callf $8,_writeh pushl $10 callf $8,_writec # asm("halt"); halt # } # } L42: ret .set L29,0x1f80 L31: subl3 $56,fp,sp jbr L32 .data #

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