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1.1 ! root 1: LL0: ! 2: .data ! 3: .set SBR,0 ! 4: .set SLR,1 ! 5: .set P0BR,2 ! 6: .set P0LR,3 ! 7: .set P1BR,4 ! 8: .set P1LR,5 ! 9: .set P2BR,6 ! 10: .set P2LR,7 ! 11: .set IPL,8 ! 12: .set MAPEN,9 ! 13: .set MME,9 ! 14: .set TBIA,10 ! 15: .set TBIS,11 ! 16: .set DCK,12 ! 17: .set CCK,13 ! 18: .set PCBB,14 ! 19: .set KSP,19 ! 20: .set USP,20 ! 21: .set CPMDCB,21 ! 22: .set PADC,25 ! 23: .set DCR,27 ! 24: .set DC_ON,1 ! 25: .set DC_OFF,2 ! 26: .set TB_ON,256 ! 27: .set TB_OFF,512 ! 28: .text ! 29: .align 1 ! 30: .globl _vl_test ! 31: _vl_test: ! 32: .word L39 ! 33: # ! 34: # ! 35: # #include "definitions" ! 36: # ! 37: # extern long iob0, iob1, iob2, iob3, ss1; ! 38: # extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7; ! 39: # extern long *p_ptr, ret_adr, exp_par0, exp_par1, exp_par2, exp_par3; ! 40: # extern long savvec3 ,act_par0, act_par1, act_par2, act_par3; ! 41: # extern long Failpc, test_va, Tpsl; ! 42: # ! 43: # vl_test() ! 44: # { long *temp; ! 45: jbr L41 ! 46: L42: ! 47: # ! 48: # if (ss1) writes("** Subtest3 : Limit and translation fault\n"); ! 49: tstl _ss1 ! 50: jeql L43 ! 51: .data 1 ! 52: L45: ! 53: .ascii "** Subtest3 : Limit and translation fault\12\0" ! 54: .text ! 55: pushl $L45 ! 56: callf $8,_writes ! 57: # temp = (long *)0; ! 58: L43: ! 59: clrl -56(fp) ! 60: # asm("mfpr $SBR,_savvec4"); ! 61: mfpr $SBR,_savvec4 ! 62: # savvec4 |= 0xc0000000; ! 63: orl2 $-1073741824,_savvec4 ! 64: # asm("mtpr _savvec4,$P0BR"); /* Double map P0 into System space */ ! 65: mtpr _savvec4,$P0BR ! 66: # asm("mfpr $SLR,_savvec4"); ! 67: mfpr $SLR,_savvec4 ! 68: # asm("mtpr _savvec4,$P0LR"); ! 69: mtpr _savvec4,$P0LR ! 70: # ! 71: # /* Set up P1PT */ ! 72: # temp = &u0p1pt; ! 73: movl $_u0p1pt,-56(fp) ! 74: # *temp = IOB2; /* 1st PTE in P1 map to IOB2 */ ! 75: andl3 $1073740800,$_iob2,r0 ! 76: shrl $10,r0,r0 ! 77: andl2 $1048575,r0 ! 78: movl r0,*-56(fp) ! 79: # savvec4 = ((long)temp) | SADDR; ! 80: orl3 $-1073741824,-56(fp),r0 ! 81: movl r0,_savvec4 ! 82: # asm("mtpr _savvec4,$P1BR"); ! 83: mtpr _savvec4,$P1BR ! 84: # asm("mtpr $1,$P1LR"); ! 85: mtpr $1,$P1LR ! 86: # ! 87: # /* Set up P2PT */ ! 88: # temp = &u0p2pt; ! 89: movl $_u0p2pt,-56(fp) ! 90: # *temp = IOB3; /* 1st PTE in P2 map to IOB3 */ ! 91: andl3 $1073740800,$_iob3,r0 ! 92: shrl $10,r0,r0 ! 93: andl2 $1048575,r0 ! 94: movl r0,*-56(fp) ! 95: # savvec4 = ((long)temp) | SADDR; ! 96: orl3 $-1073741824,-56(fp),r0 ! 97: movl r0,_savvec4 ! 98: # savvec4 -= (LAST_VPGNO << 2); ! 99: subl2 $4194300,_savvec4 ! 100: # asm("mtpr _savvec4, $P2BR"); ! 101: mtpr _savvec4, $P2BR ! 102: # asm("mtpr $0xffffe, $P2LR"); /* Use only 1 entry */ ! 103: mtpr $0xffffe, $P2LR ! 104: # ! 105: # asm("mtpr $0,$TBIA"); ! 106: mtpr $0,$TBIA ! 107: # asm("mtpr $0,$PADC"); ! 108: mtpr $0,$PADC ! 109: # asm("mtpr $1,$MME"); ! 110: mtpr $1,$MME ! 111: # asm("jmp *$0f"); /* Go virtual */ ! 112: jmp *$0f ! 113: # asm("0:"); ! 114: 0: ! 115: # limit_chk(); /* Limit test */ ! 116: callf $4,_limit_chk ! 117: # vbit_chk(); /* valid bit test */ ! 118: callf $4,_vbit_chk ! 119: # ! 120: # asm("mtpr $0,$MME"); /* back to physical */ ! 121: mtpr $0,$MME ! 122: # asm("mtpr $0,$P0LR"); /* Invalidate P0 space */ ! 123: mtpr $0,$P0LR ! 124: # } ! 125: ret ! 126: .set L39,0x0 ! 127: L41: ! 128: subl3 $56,fp,sp ! 129: jbr L42 ! 130: .data ! 131: .text ! 132: .align 1 ! 133: .globl _limit_chk ! 134: _limit_chk: ! 135: .word L48 ! 136: # ! 137: # ! 138: # limit_chk() ! 139: # /* this test will validate that TAHOE will detect any off limit ! 140: # access to SPT, P0PT, P1PT, P2PT. ! 141: # */ ! 142: # { ! 143: jbr L50 ! 144: L51: ! 145: # long sys_vadr, fault_vadr, pte_ref, fault_type; ! 146: # ! 147: # length_chk(SLR, SADDR); /* Test on SPT */ ! 148: pushl $-1073741824 ! 149: pushl $1 ! 150: callf $12,_length_chk ! 151: # length_chk(P0LR, P0ADDR); /* Test on P0PT */ ! 152: pushl $0 ! 153: pushl $3 ! 154: callf $12,_length_chk ! 155: # length_chk(P1LR, P1ADDR); /* Test on P1PT */ ! 156: pushl $1073741824 ! 157: pushl $5 ! 158: callf $12,_length_chk ! 159: # length_chk(P2LR, P2ADDR); /* Test on P2PT */ ! 160: pushl $-2147483648 ! 161: pushl $7 ! 162: callf $12,_length_chk ! 163: # ! 164: # /* Check limit fault on SPT when access P1 space */ ! 165: # asm("mfpr $P1LR,_savvec7"); /* save P1LR */ ! 166: mfpr $P1LR,_savvec7 ! 167: # asm("mtpr $0x1ffff,$P1LR"); /* set P1LR to very large value */ ! 168: mtpr $0x1ffff,$P1LR ! 169: # ! 170: # asm("mfpr $SLR,_savvec4"); ! 171: mfpr $SLR,_savvec4 ! 172: # sys_vadr = ((savvec4+1) << PGSHIFT) | SADDR; ! 173: addl3 $1,_savvec4,r0 ! 174: shll $10,r0,r0 ! 175: orl2 $-1073741824,r0 ! 176: movl r0,-56(fp) ! 177: # asm("mfpr $P1BR,_savvec4"); ! 178: mfpr $P1BR,_savvec4 ! 179: # fault_vadr = (((unsigned)(sys_vadr-savvec4) >> 2) << PGSHIFT) | P1ADDR; ! 180: subl3 _savvec4,-56(fp),r0 ! 181: shrl $2,r0,r0 ! 182: shll $10,r0,r0 ! 183: orl2 $1073741824,r0 ! 184: movl r0,-60(fp) ! 185: # pte_ref = TRUE; ! 186: movl $1,-64(fp) ! 187: # fault_type = LENGTH; ! 188: movl $1,-68(fp) ! 189: # lmt_fault(fault_vadr, pte_ref, fault_type); ! 190: pushl -68(fp) ! 191: pushl -64(fp) ! 192: pushl -60(fp) ! 193: callf $16,_lmt_fault ! 194: # ! 195: # /* restore original SLR, P1LR */ ! 196: # asm("mtpr _savvec7,$P1LR"); ! 197: mtpr _savvec7,$P1LR ! 198: # } ! 199: ret ! 200: .set L48,0x0 ! 201: L50: ! 202: subl3 $68,fp,sp ! 203: jbr L51 ! 204: .data ! 205: .text ! 206: .align 1 ! 207: .globl _length_chk ! 208: _length_chk: ! 209: .word L54 ! 210: # ! 211: # length_chk(table, space) ! 212: # long table, space; ! 213: # { long fault_vadr, pte_ref, fault_type; ! 214: jbr L56 ! 215: L57: ! 216: # ! 217: # savvec6 = table; ! 218: movl 4(fp),_savvec6 ! 219: # asm("mfpr _savvec6,_savvec4"); /* Get length of table */ ! 220: mfpr _savvec6,_savvec4 ! 221: # if (table==P2LR) savvec4--; ! 222: cmpl 4(fp),$7 ! 223: jneq L58 ! 224: decl _savvec4 ! 225: # else savvec4++; ! 226: jbr L59 ! 227: L58: ! 228: incl _savvec4 ! 229: L59: ! 230: # fault_vadr = (savvec4<<PGSHIFT)|space; ! 231: shll $10,_savvec4,r0 ! 232: orl2 8(fp),r0 ! 233: movl r0,-56(fp) ! 234: # fault_type = LENGTH; ! 235: movl $1,-64(fp) ! 236: # pte_ref = FALSE; ! 237: clrl -60(fp) ! 238: # lmt_fault(fault_vadr, pte_ref, fault_type); ! 239: pushl -64(fp) ! 240: pushl -60(fp) ! 241: pushl -56(fp) ! 242: callf $16,_lmt_fault ! 243: # ! 244: # } ! 245: ret ! 246: .set L54,0x0 ! 247: L56: ! 248: subl3 $64,fp,sp ! 249: jbr L57 ! 250: .data ! 251: .text ! 252: .align 1 ! 253: .globl _vbit_chk ! 254: _vbit_chk: ! 255: .word L60 ! 256: # ! 257: # ! 258: # vbit_chk() ! 259: # /* This test force translation not valid fault on SPT, P0PT, ! 260: # P1PT, P2PT. ! 261: # */ ! 262: # { ! 263: jbr L62 ! 264: L63: ! 265: # long fault_vadr, t_pgno, *pt_base, fault_type, pte_ref; ! 266: # long saved_p1lr; ! 267: # ! 268: # valid_chk(SBR, TEST_PTESYS, SADDR); /* Test on SPT */ ! 269: pushl $-1073741824 ! 270: pushl _unused ! 271: pushl $0 ! 272: callf $16,_valid_chk ! 273: # valid_chk(P0BR, TEST_PTEP0, P0ADDR); /* Test on P0PT */ ! 274: pushl $0 ! 275: pushl $68 ! 276: pushl $2 ! 277: callf $16,_valid_chk ! 278: # valid_chk(P1BR, TEST_PTEP1, P1ADDR); /* Test on P1PT */ ! 279: pushl $1073741824 ! 280: pushl $0 ! 281: pushl $4 ! 282: callf $16,_valid_chk ! 283: # valid_chk(P2BR, TEST_PTEP2, P2ADDR); /* Test on P2PT */ ! 284: pushl $-2147483648 ! 285: pushl $1048575 ! 286: pushl $6 ! 287: callf $16,_valid_chk ! 288: # ! 289: # /* Check translation not valid fault on SPT when access P1 space */ ! 290: # ! 291: # asm("mfpr $P1LR,_savvec5"); ! 292: mfpr $P1LR,_savvec5 ! 293: # saved_p1lr = savvec5; /* save P1LR */ ! 294: movl _savvec5,-76(fp) ! 295: # asm("mtpr $768,$P1LR"); /* Set P1LR to have 768 PTEs which */ ! 296: mtpr $768,$P1LR ! 297: # /* is 3 page long. */ ! 298: # /* Virtual addr used to force the fault will need PTE #512 in P1PT */ ! 299: # fault_vadr = (long)((512<<PGSHIFT)|P1ADDR); ! 300: movl $1074266112,-56(fp) ! 301: # /* invalidate PTE in SPT which map 3rd page of P1PT */ ! 302: # asm("mfpr $SBR,_savvec5"); ! 303: mfpr $SBR,_savvec5 ! 304: # pt_base = (long *)savvec5; ! 305: movl _savvec5,-64(fp) ! 306: # t_pgno = (U0_P1PT) + 2; ! 307: andl3 $1073740800,$_u0p1pt,r0 ! 308: shrl $10,r0,r0 ! 309: andl2 $1048575,r0 ! 310: addl2 $2,r0 ! 311: movl r0,-60(fp) ! 312: # pt_base += t_pgno; /* address of PTE in SPT that */ ! 313: shll $2,-60(fp),r0 ! 314: addl2 r0,-64(fp) ! 315: # /* mapped the 3rd page of P1PT */ ! 316: # *pt_base = *pt_base & 0x7fffffff; /* Turn off valid bit */ ! 317: andl3 $2147483647,*-64(fp),r0 ! 318: movl r0,*-64(fp) ! 319: # ! 320: # fault_type = VALID; ! 321: clrl -68(fp) ! 322: # pte_ref = TRUE; ! 323: movl $1,-72(fp) ! 324: # lmt_fault(fault_vadr, pte_ref, fault_type); ! 325: pushl -68(fp) ! 326: pushl -72(fp) ! 327: pushl -56(fp) ! 328: callf $16,_lmt_fault ! 329: # ! 330: # /* restore original SLR, P1LR */ ! 331: # *pt_base = *pt_base | 0x80000000; /* Turn on valid bit */ ! 332: orl3 $-2147483648,*-64(fp),r0 ! 333: movl r0,*-64(fp) ! 334: # savvec5 = saved_p1lr; ! 335: movl -76(fp),_savvec5 ! 336: # asm("mtpr _savvec5,$P1LR"); ! 337: mtpr _savvec5,$P1LR ! 338: # } ! 339: ret ! 340: .set L60,0x0 ! 341: L62: ! 342: subl3 $76,fp,sp ! 343: jbr L63 ! 344: .data ! 345: .text ! 346: .align 1 ! 347: .globl _valid_chk ! 348: _valid_chk: ! 349: .word L65 ! 350: # ! 351: # valid_chk(table, test_pte, space) ! 352: # long table, test_pte, space; ! 353: # { long *pt_base, saved_pte, fault_vadr, pte_ref, fault_type; ! 354: jbr L67 ! 355: L68: ! 356: # ! 357: # savvec6 = table; ! 358: movl 4(fp),_savvec6 ! 359: # asm("mfpr _savvec6,_savvec5"); ! 360: mfpr _savvec6,_savvec5 ! 361: # pt_base = (long *)savvec5; ! 362: movl _savvec5,-56(fp) ! 363: # pt_base += test_pte; /* address of test PTE */ ! 364: shll $2,8(fp),r0 ! 365: addl2 r0,-56(fp) ! 366: # fault_vadr = (test_pte<<PGSHIFT)|space; ! 367: shll $10,8(fp),r0 ! 368: orl2 12(fp),r0 ! 369: movl r0,-64(fp) ! 370: # saved_pte = *pt_base; /* save original PTE */ ! 371: movl *-56(fp),-60(fp) ! 372: # /* Turn off valid bit and set access to User,Kernel R/W */ ! 373: # *pt_base = (*pt_base & 0x7ffffff) | PTE_UW; ! 374: andl3 $134217727,*-56(fp),r0 ! 375: orl2 $2013265920,r0 ! 376: movl r0,*-56(fp) ! 377: # fault_type = VALID; ! 378: clrl -72(fp) ! 379: # pte_ref = FALSE; ! 380: clrl -68(fp) ! 381: # lmt_fault(fault_vadr, pte_ref, fault_type); ! 382: pushl -72(fp) ! 383: pushl -68(fp) ! 384: pushl -64(fp) ! 385: callf $16,_lmt_fault ! 386: # *pt_base = saved_pte; /* Restore original PTE */ ! 387: movl -60(fp),*-56(fp) ! 388: # } ! 389: ret ! 390: .set L65,0x0 ! 391: L67: ! 392: subl3 $72,fp,sp ! 393: jbr L68 ! 394: .data ! 395: .text ! 396: .align 1 ! 397: .globl _lmt_fault ! 398: _lmt_fault: ! 399: .word L69 ! 400: # ! 401: # ! 402: # /* Force limit and valid fault */ ! 403: # ! 404: # lmt_fault(fault_vadr, pte_ref, fault_type) ! 405: # long fault_vadr, pte_ref, fault_type; ! 406: # { ! 407: jbr L71 ! 408: L72: ! 409: # long saved_vec, *scb_base, lx, *lptr, access; ! 410: # ! 411: # scb_base = &scb; ! 412: movl $_scb,-60(fp) ! 413: # if (fault_type == LENGTH) ! 414: cmpl 12(fp),$1 ! 415: jneq L73 ! 416: # { ! 417: # scb_base += PROT_VEC; ! 418: addl2 $188,-60(fp) ! 419: # ! 420: # /* Make new PTE : If this logic "mkpte" is taken out */ ! 421: # /* and this test passed that imply TAHOE will generate */ ! 422: # /* limit fault before access prot. and translation not */ ! 423: # /* valid fault. */ ! 424: # ! 425: # if (pte_ref==FALSE) mkpte(fault_vadr); ! 426: tstl 8(fp) ! 427: jneq L74 ! 428: pushl 4(fp) ! 429: callf $8,_mkpte ! 430: # } ! 431: L74: ! 432: # else scb_base += TRANS_VEC; ! 433: jbr L76 ! 434: L73: ! 435: addl2 $192,-60(fp) ! 436: L76: ! 437: # ! 438: # saved_vec = *scb_base; /* save old protection fault vector */ ! 439: movl *-60(fp),-56(fp) ! 440: # asm("movab handler1,_savvec4"); ! 441: movab handler1,_savvec4 ! 442: # ! 443: # exp_par1 = fault_vadr; /* Set up expect fault parameters */ ! 444: movl 4(fp),_exp_par1 ! 445: # test_va = exp_par1; ! 446: movl _exp_par1,_test_va ! 447: # asm("movpsl _exp_par3"); /* PSL at time of fault */ ! 448: movpsl _exp_par3 ! 449: # exp_par3 &= 0xffffffc0; /* Mask out PSW flags */ ! 450: andl2 $-64,_exp_par3 ! 451: # Tpsl = exp_par3; ! 452: movl _exp_par3,_Tpsl ! 453: # asm("movab okret,_ret_adr"); ! 454: movab okret,_ret_adr ! 455: # for (access = READ; access <= WRITE; access++) ! 456: clrl -72(fp) ! 457: L79: ! 458: cmpl -72(fp),$1 ! 459: jgtr L78 ! 460: # { ! 461: # /* length ,R/W violation */ ! 462: # if (fault_type == LENGTH) ! 463: cmpl 12(fp),$1 ! 464: jneq L80 ! 465: # exp_par0 = 1 | (access<<2) | (pte_ref<<1); ! 466: shll $2,-72(fp),r0 ! 467: orl2 $1,r0 ! 468: shll $1,8(fp),r1 ! 469: orl2 r1,r0 ! 470: movl r0,_exp_par0 ! 471: # else ! 472: jbr L81 ! 473: L80: ! 474: # exp_par0 = (access<<2) | (pte_ref<<1); ! 475: shll $2,-72(fp),r0 ! 476: shll $1,8(fp),r1 ! 477: orl2 r1,r0 ! 478: movl r0,_exp_par0 ! 479: L81: ! 480: # *scb_base = savvec4; /* Set new handler */ ! 481: movl _savvec4,*-60(fp) ! 482: # asm("movl _exp_par1,r0"); ! 483: movl _exp_par1,r0 ! 484: # if (access==WRITE) ! 485: cmpl -72(fp),$1 ! 486: jneq L82 ! 487: # { ! 488: # asm("movab pc_fault1,_exp_par2"); /* PC at fault */ ! 489: movab pc_fault1,_exp_par2 ! 490: # Failpc = exp_par2; ! 491: movl _exp_par2,_Failpc ! 492: # asm("pc_fault1:"); ! 493: pc_fault1: ! 494: # asm("movl $0,(r0)"); /* Try with write access */ ! 495: movl $0,(r0) ! 496: # } ! 497: # else ! 498: jbr L83 ! 499: L82: ! 500: # { ! 501: # asm("movab pc_fault2,_exp_par2"); /* PC at fault */ ! 502: movab pc_fault2,_exp_par2 ! 503: # Failpc = exp_par2; ! 504: movl _exp_par2,_Failpc ! 505: # asm("pc_fault2:"); ! 506: pc_fault2: ! 507: # asm("movl (r0),r12"); /* Try with read access */ ! 508: movl (r0),r12 ! 509: # } ! 510: L83: ! 511: # /* Error if program comes to this point */ ! 512: # if (fault_type == LENGTH) ! 513: cmpl 12(fp),$1 ! 514: jneq L84 ! 515: # writes("** Expected limit fault didnot happen\n"); ! 516: .data 1 ! 517: L85: ! 518: .ascii "** Expected limit fault didnot happen\12\0" ! 519: .text ! 520: pushl $L85 ! 521: callf $8,_writes ! 522: # else ! 523: jbr L86 ! 524: L84: ! 525: # writes("** Expected translation fault didnot happen\n"); ! 526: .data 1 ! 527: L87: ! 528: .ascii "** Expected translation fault didnot happen\12\0" ! 529: .text ! 530: pushl $L87 ! 531: callf $8,_writes ! 532: L86: ! 533: # ac_error1(); ! 534: callf $4,_ac_error1 ! 535: # *scb_base = saved_vec; /* Restore ILL_ACCESS vector */ ! 536: movl -56(fp),*-60(fp) ! 537: # asm("halt"); ! 538: halt ! 539: # asm("okret:"); ! 540: okret: ! 541: # *scb_base = saved_vec; /* Restore ILL_ACCESS vector */ ! 542: movl -56(fp),*-60(fp) ! 543: # if (fault_type == LENGTH) ! 544: cmpl 12(fp),$1 ! 545: jneq L89 ! 546: # chk_fpars("** Page Table Limit exception\n"); ! 547: .data 1 ! 548: L91: ! 549: .ascii "** Page Table Limit exception\12\0" ! 550: .text ! 551: pushl $L91 ! 552: callf $8,_chk_fpars ! 553: # else ! 554: jbr L92 ! 555: L89: ! 556: # chk_fpars("** Translation not valid exception\n"); ! 557: .data 1 ! 558: L93: ! 559: .ascii "** Translation not valid exception\12\0" ! 560: .text ! 561: pushl $L93 ! 562: callf $8,_chk_fpars ! 563: L92: ! 564: # } ! 565: L77: ! 566: incl -72(fp) ! 567: jbr L79 ! 568: L78: ! 569: # } ! 570: ret ! 571: .set L69,0x0 ! 572: L71: ! 573: subl3 $72,fp,sp ! 574: jbr L72 ! 575: .data ! 576: .text ! 577: .align 1 ! 578: .globl _mkpte ! 579: _mkpte: ! 580: .word L94 ! 581: # ! 582: # mkpte(flt_vadr) ! 583: # long flt_vadr; ! 584: # { long space, oldpte, pteno, regno; ! 585: jbr L96 ! 586: L97: ! 587: # ! 588: # space = (flt_vadr >> 30) & 0x3; ! 589: shar $30,4(fp),r0 ! 590: andl2 $3,r0 ! 591: movl r0,-56(fp) ! 592: # pteno = (flt_vadr >> PGSHIFT) & 0xfffff; ! 593: shar $10,4(fp),r0 ! 594: andl2 $1048575,r0 ! 595: movl r0,-64(fp) ! 596: # if (space==3) regno = SBR; /* System */ ! 597: cmpl -56(fp),$3 ! 598: jneq L98 ! 599: clrl -68(fp) ! 600: # if (space==2) { regno = P2BR; /* P2 */ ! 601: L98: ! 602: cmpl -56(fp),$2 ! 603: jneq L99 ! 604: movl $6,-68(fp) ! 605: # pteno = LAST_VPGNO - 2; } ! 606: movl $1048573,-64(fp) ! 607: # if (space==1) regno = P1BR; /* P1 */ ! 608: L99: ! 609: cmpl -56(fp),$1 ! 610: jneq L100 ! 611: movl $4,-68(fp) ! 612: # if (space==0) regno = P0BR; /* P0 */ ! 613: L100: ! 614: tstl -56(fp) ! 615: jneq L101 ! 616: movl $2,-68(fp) ! 617: # ! 618: # /* All access, V_BIT on */ ! 619: # fixpv_pte(regno,pteno,&oldpte,PTE_KW | PTE_V); ! 620: L101: ! 621: pushl $-536870912 ! 622: subl3 $60,fp,r0 ! 623: pushl r0 ! 624: pushl -64(fp) ! 625: pushl -68(fp) ! 626: callf $20,_fixpv_pte ! 627: # ! 628: # } ! 629: ret ! 630: .set L94,0x0 ! 631: L96: ! 632: subl3 $68,fp,sp ! 633: jbr L97 ! 634: .data ! 635: .text ! 636: .align 1 ! 637: .globl _prot_handler ! 638: _prot_handler: ! 639: .word L104 ! 640: # ! 641: # prot_handler() ! 642: # { ! 643: jbr L106 ! 644: L107: ! 645: # asm(".align 2"); ! 646: .align 2 ! 647: # asm("handler1:"); ! 648: handler1: ! 649: # asm("movab _act_par0,_p_ptr"); /* Set pointer to fault parameters */ ! 650: movab _act_par0,_p_ptr ! 651: # asm("movl (sp)+,_act_par0"); ! 652: movl (sp)+,_act_par0 ! 653: # asm("movl (sp)+,_act_par1"); ! 654: movl (sp)+,_act_par1 ! 655: # asm("movl (sp)+,_act_par2"); ! 656: movl (sp)+,_act_par2 ! 657: # asm("movl (sp)+,_act_par3"); ! 658: movl (sp)+,_act_par3 ! 659: # asm("jmp *_ret_adr"); ! 660: jmp *_ret_adr ! 661: # } ! 662: ret ! 663: .set L104,0x0 ! 664: L106: ! 665: jbr L107 ! 666: .data ! 667: #
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