cci/d/memman/vbit_limit.s - view

File: [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / memman / vbit_limit.s
Revision 1.1.1.1 (vendor branch): download - view: text, annotated - select for diffs
Sun Jul 28 12:24:19 2019 UTC (6 years, 11 months ago) by root
Branches: bsd, MAIN
CVS tags: v12b, v121, HEAD

Power 6/32 Unix version 1.2b

LL0: .data .set SBR,0 .set SLR,1 .set P0BR,2 .set P0LR,3 .set P1BR,4 .set P1LR,5 .set P2BR,6 .set P2LR,7 .set IPL,8 .set MAPEN,9 .set MME,9 .set TBIA,10 .set TBIS,11 .set DCK,12 .set CCK,13 .set PCBB,14 .set KSP,19 .set USP,20 .set CPMDCB,21 .set PADC,25 .set DCR,27 .set DC_ON,1 .set DC_OFF,2 .set TB_ON,256 .set TB_OFF,512 .text .align 1 .globl _vl_test _vl_test: .word L39 # # # #include "definitions" # # extern long iob0, iob1, iob2, iob3, ss1; # extern long unused, u0p1pt, u0p2pt, scb, savvec4, savvec5, savvec6, savvec7; # extern long *p_ptr, ret_adr, exp_par0, exp_par1, exp_par2, exp_par3; # extern long savvec3 ,act_par0, act_par1, act_par2, act_par3; # extern long Failpc, test_va, Tpsl; # # vl_test() # { long *temp; jbr L41 L42: # # if (ss1) writes("** Subtest3 : Limit and translation fault\n"); tstl _ss1 jeql L43 .data 1 L45: .ascii "** Subtest3 : Limit and translation fault\12\0" .text pushl $L45 callf $8,_writes # temp = (long *)0; L43: clrl -56(fp) # asm("mfpr $SBR,_savvec4"); mfpr $SBR,_savvec4 # savvec4 |= 0xc0000000; orl2 $-1073741824,_savvec4 # asm("mtpr _savvec4,$P0BR"); /* Double map P0 into System space */ mtpr _savvec4,$P0BR # asm("mfpr $SLR,_savvec4"); mfpr $SLR,_savvec4 # asm("mtpr _savvec4,$P0LR"); mtpr _savvec4,$P0LR # # /* Set up P1PT */ # temp = &u0p1pt; movl $_u0p1pt,-56(fp) # *temp = IOB2; /* 1st PTE in P1 map to IOB2 */ andl3 $1073740800,$_iob2,r0 shrl $10,r0,r0 andl2 $1048575,r0 movl r0,*-56(fp) # savvec4 = ((long)temp) | SADDR; orl3 $-1073741824,-56(fp),r0 movl r0,_savvec4 # asm("mtpr _savvec4,$P1BR"); mtpr _savvec4,$P1BR # asm("mtpr $1,$P1LR"); mtpr $1,$P1LR # # /* Set up P2PT */ # temp = &u0p2pt; movl $_u0p2pt,-56(fp) # *temp = IOB3; /* 1st PTE in P2 map to IOB3 */ andl3 $1073740800,$_iob3,r0 shrl $10,r0,r0 andl2 $1048575,r0 movl r0,*-56(fp) # savvec4 = ((long)temp) | SADDR; orl3 $-1073741824,-56(fp),r0 movl r0,_savvec4 # savvec4 -= (LAST_VPGNO << 2); subl2 $4194300,_savvec4 # asm("mtpr _savvec4, $P2BR"); mtpr _savvec4, $P2BR # asm("mtpr $0xffffe, $P2LR"); /* Use only 1 entry */ mtpr $0xffffe, $P2LR # # asm("mtpr $0,$TBIA"); mtpr $0,$TBIA # asm("mtpr $0,$PADC"); mtpr $0,$PADC # asm("mtpr $1,$MME"); mtpr $1,$MME # asm("jmp *$0f"); /* Go virtual */ jmp *$0f # asm("0:"); 0: # limit_chk(); /* Limit test */ callf $4,_limit_chk # vbit_chk(); /* valid bit test */ callf $4,_vbit_chk # # asm("mtpr $0,$MME"); /* back to physical */ mtpr $0,$MME # asm("mtpr $0,$P0LR"); /* Invalidate P0 space */ mtpr $0,$P0LR # } ret .set L39,0x0 L41: subl3 $56,fp,sp jbr L42 .data .text .align 1 .globl _limit_chk _limit_chk: .word L48 # # # limit_chk() # /* this test will validate that TAHOE will detect any off limit # access to SPT, P0PT, P1PT, P2PT. # */ # { jbr L50 L51: # long sys_vadr, fault_vadr, pte_ref, fault_type; # # length_chk(SLR, SADDR); /* Test on SPT */ pushl $-1073741824 pushl $1 callf $12,_length_chk # length_chk(P0LR, P0ADDR); /* Test on P0PT */ pushl $0 pushl $3 callf $12,_length_chk # length_chk(P1LR, P1ADDR); /* Test on P1PT */ pushl $1073741824 pushl $5 callf $12,_length_chk # length_chk(P2LR, P2ADDR); /* Test on P2PT */ pushl $-2147483648 pushl $7 callf $12,_length_chk # # /* Check limit fault on SPT when access P1 space */ # asm("mfpr $P1LR,_savvec7"); /* save P1LR */ mfpr $P1LR,_savvec7 # asm("mtpr $0x1ffff,$P1LR"); /* set P1LR to very large value */ mtpr $0x1ffff,$P1LR # # asm("mfpr $SLR,_savvec4"); mfpr $SLR,_savvec4 # sys_vadr = ((savvec4+1) << PGSHIFT) | SADDR; addl3 $1,_savvec4,r0 shll $10,r0,r0 orl2 $-1073741824,r0 movl r0,-56(fp) # asm("mfpr $P1BR,_savvec4"); mfpr $P1BR,_savvec4 # fault_vadr = (((unsigned)(sys_vadr-savvec4) >> 2) << PGSHIFT) | P1ADDR; subl3 _savvec4,-56(fp),r0 shrl $2,r0,r0 shll $10,r0,r0 orl2 $1073741824,r0 movl r0,-60(fp) # pte_ref = TRUE; movl $1,-64(fp) # fault_type = LENGTH; movl $1,-68(fp) # lmt_fault(fault_vadr, pte_ref, fault_type); pushl -68(fp) pushl -64(fp) pushl -60(fp) callf $16,_lmt_fault # # /* restore original SLR, P1LR */ # asm("mtpr _savvec7,$P1LR"); mtpr _savvec7,$P1LR # } ret .set L48,0x0 L50: subl3 $68,fp,sp jbr L51 .data .text .align 1 .globl _length_chk _length_chk: .word L54 # # length_chk(table, space) # long table, space; # { long fault_vadr, pte_ref, fault_type; jbr L56 L57: # # savvec6 = table; movl 4(fp),_savvec6 # asm("mfpr _savvec6,_savvec4"); /* Get length of table */ mfpr _savvec6,_savvec4 # if (table==P2LR) savvec4--; cmpl 4(fp),$7 jneq L58 decl _savvec4 # else savvec4++; jbr L59 L58: incl _savvec4 L59: # fault_vadr = (savvec4<<PGSHIFT)|space; shll $10,_savvec4,r0 orl2 8(fp),r0 movl r0,-56(fp) # fault_type = LENGTH; movl $1,-64(fp) # pte_ref = FALSE; clrl -60(fp) # lmt_fault(fault_vadr, pte_ref, fault_type); pushl -64(fp) pushl -60(fp) pushl -56(fp) callf $16,_lmt_fault # # } ret .set L54,0x0 L56: subl3 $64,fp,sp jbr L57 .data .text .align 1 .globl _vbit_chk _vbit_chk: .word L60 # # # vbit_chk() # /* This test force translation not valid fault on SPT, P0PT, # P1PT, P2PT. # */ # { jbr L62 L63: # long fault_vadr, t_pgno, *pt_base, fault_type, pte_ref; # long saved_p1lr; # # valid_chk(SBR, TEST_PTESYS, SADDR); /* Test on SPT */ pushl $-1073741824 pushl _unused pushl $0 callf $16,_valid_chk # valid_chk(P0BR, TEST_PTEP0, P0ADDR); /* Test on P0PT */ pushl $0 pushl $68 pushl $2 callf $16,_valid_chk # valid_chk(P1BR, TEST_PTEP1, P1ADDR); /* Test on P1PT */ pushl $1073741824 pushl $0 pushl $4 callf $16,_valid_chk # valid_chk(P2BR, TEST_PTEP2, P2ADDR); /* Test on P2PT */ pushl $-2147483648 pushl $1048575 pushl $6 callf $16,_valid_chk # # /* Check translation not valid fault on SPT when access P1 space */ # # asm("mfpr $P1LR,_savvec5"); mfpr $P1LR,_savvec5 # saved_p1lr = savvec5; /* save P1LR */ movl _savvec5,-76(fp) # asm("mtpr $768,$P1LR"); /* Set P1LR to have 768 PTEs which */ mtpr $768,$P1LR # /* is 3 page long. */ # /* Virtual addr used to force the fault will need PTE #512 in P1PT */ # fault_vadr = (long)((512<<PGSHIFT)|P1ADDR); movl $1074266112,-56(fp) # /* invalidate PTE in SPT which map 3rd page of P1PT */ # asm("mfpr $SBR,_savvec5"); mfpr $SBR,_savvec5 # pt_base = (long *)savvec5; movl _savvec5,-64(fp) # t_pgno = (U0_P1PT) + 2; andl3 $1073740800,$_u0p1pt,r0 shrl $10,r0,r0 andl2 $1048575,r0 addl2 $2,r0 movl r0,-60(fp) # pt_base += t_pgno; /* address of PTE in SPT that */ shll $2,-60(fp),r0 addl2 r0,-64(fp) # /* mapped the 3rd page of P1PT */ # *pt_base = *pt_base & 0x7fffffff; /* Turn off valid bit */ andl3 $2147483647,*-64(fp),r0 movl r0,*-64(fp) # # fault_type = VALID; clrl -68(fp) # pte_ref = TRUE; movl $1,-72(fp) # lmt_fault(fault_vadr, pte_ref, fault_type); pushl -68(fp) pushl -72(fp) pushl -56(fp) callf $16,_lmt_fault # # /* restore original SLR, P1LR */ # *pt_base = *pt_base | 0x80000000; /* Turn on valid bit */ orl3 $-2147483648,*-64(fp),r0 movl r0,*-64(fp) # savvec5 = saved_p1lr; movl -76(fp),_savvec5 # asm("mtpr _savvec5,$P1LR"); mtpr _savvec5,$P1LR # } ret .set L60,0x0 L62: subl3 $76,fp,sp jbr L63 .data .text .align 1 .globl _valid_chk _valid_chk: .word L65 # # valid_chk(table, test_pte, space) # long table, test_pte, space; # { long *pt_base, saved_pte, fault_vadr, pte_ref, fault_type; jbr L67 L68: # # savvec6 = table; movl 4(fp),_savvec6 # asm("mfpr _savvec6,_savvec5"); mfpr _savvec6,_savvec5 # pt_base = (long *)savvec5; movl _savvec5,-56(fp) # pt_base += test_pte; /* address of test PTE */ shll $2,8(fp),r0 addl2 r0,-56(fp) # fault_vadr = (test_pte<<PGSHIFT)|space; shll $10,8(fp),r0 orl2 12(fp),r0 movl r0,-64(fp) # saved_pte = *pt_base; /* save original PTE */ movl *-56(fp),-60(fp) # /* Turn off valid bit and set access to User,Kernel R/W */ # *pt_base = (*pt_base & 0x7ffffff) | PTE_UW; andl3 $134217727,*-56(fp),r0 orl2 $2013265920,r0 movl r0,*-56(fp) # fault_type = VALID; clrl -72(fp) # pte_ref = FALSE; clrl -68(fp) # lmt_fault(fault_vadr, pte_ref, fault_type); pushl -72(fp) pushl -68(fp) pushl -64(fp) callf $16,_lmt_fault # *pt_base = saved_pte; /* Restore original PTE */ movl -60(fp),*-56(fp) # } ret .set L65,0x0 L67: subl3 $72,fp,sp jbr L68 .data .text .align 1 .globl _lmt_fault _lmt_fault: .word L69 # # # /* Force limit and valid fault */ # # lmt_fault(fault_vadr, pte_ref, fault_type) # long fault_vadr, pte_ref, fault_type; # { jbr L71 L72: # long saved_vec, *scb_base, lx, *lptr, access; # # scb_base = &scb; movl $_scb,-60(fp) # if (fault_type == LENGTH) cmpl 12(fp),$1 jneq L73 # { # scb_base += PROT_VEC; addl2 $188,-60(fp) # # /* Make new PTE : If this logic "mkpte" is taken out */ # /* and this test passed that imply TAHOE will generate */ # /* limit fault before access prot. and translation not */ # /* valid fault. */ # # if (pte_ref==FALSE) mkpte(fault_vadr); tstl 8(fp) jneq L74 pushl 4(fp) callf $8,_mkpte # } L74: # else scb_base += TRANS_VEC; jbr L76 L73: addl2 $192,-60(fp) L76: # # saved_vec = *scb_base; /* save old protection fault vector */ movl *-60(fp),-56(fp) # asm("movab handler1,_savvec4"); movab handler1,_savvec4 # # exp_par1 = fault_vadr; /* Set up expect fault parameters */ movl 4(fp),_exp_par1 # test_va = exp_par1; movl _exp_par1,_test_va # asm("movpsl _exp_par3"); /* PSL at time of fault */ movpsl _exp_par3 # exp_par3 &= 0xffffffc0; /* Mask out PSW flags */ andl2 $-64,_exp_par3 # Tpsl = exp_par3; movl _exp_par3,_Tpsl # asm("movab okret,_ret_adr"); movab okret,_ret_adr # for (access = READ; access <= WRITE; access++) clrl -72(fp) L79: cmpl -72(fp),$1 jgtr L78 # { # /* length ,R/W violation */ # if (fault_type == LENGTH) cmpl 12(fp),$1 jneq L80 # exp_par0 = 1 | (access<<2) | (pte_ref<<1); shll $2,-72(fp),r0 orl2 $1,r0 shll $1,8(fp),r1 orl2 r1,r0 movl r0,_exp_par0 # else jbr L81 L80: # exp_par0 = (access<<2) | (pte_ref<<1); shll $2,-72(fp),r0 shll $1,8(fp),r1 orl2 r1,r0 movl r0,_exp_par0 L81: # *scb_base = savvec4; /* Set new handler */ movl _savvec4,*-60(fp) # asm("movl _exp_par1,r0"); movl _exp_par1,r0 # if (access==WRITE) cmpl -72(fp),$1 jneq L82 # { # asm("movab pc_fault1,_exp_par2"); /* PC at fault */ movab pc_fault1,_exp_par2 # Failpc = exp_par2; movl _exp_par2,_Failpc # asm("pc_fault1:"); pc_fault1: # asm("movl $0,(r0)"); /* Try with write access */ movl $0,(r0) # } # else jbr L83 L82: # { # asm("movab pc_fault2,_exp_par2"); /* PC at fault */ movab pc_fault2,_exp_par2 # Failpc = exp_par2; movl _exp_par2,_Failpc # asm("pc_fault2:"); pc_fault2: # asm("movl (r0),r12"); /* Try with read access */ movl (r0),r12 # } L83: # /* Error if program comes to this point */ # if (fault_type == LENGTH) cmpl 12(fp),$1 jneq L84 # writes("** Expected limit fault didnot happen\n"); .data 1 L85: .ascii "** Expected limit fault didnot happen\12\0" .text pushl $L85 callf $8,_writes # else jbr L86 L84: # writes("** Expected translation fault didnot happen\n"); .data 1 L87: .ascii "** Expected translation fault didnot happen\12\0" .text pushl $L87 callf $8,_writes L86: # ac_error1(); callf $4,_ac_error1 # *scb_base = saved_vec; /* Restore ILL_ACCESS vector */ movl -56(fp),*-60(fp) # asm("halt"); halt # asm("okret:"); okret: # *scb_base = saved_vec; /* Restore ILL_ACCESS vector */ movl -56(fp),*-60(fp) # if (fault_type == LENGTH) cmpl 12(fp),$1 jneq L89 # chk_fpars("** Page Table Limit exception\n"); .data 1 L91: .ascii "** Page Table Limit exception\12\0" .text pushl $L91 callf $8,_chk_fpars # else jbr L92 L89: # chk_fpars("** Translation not valid exception\n"); .data 1 L93: .ascii "** Translation not valid exception\12\0" .text pushl $L93 callf $8,_chk_fpars L92: # } L77: incl -72(fp) jbr L79 L78: # } ret .set L69,0x0 L71: subl3 $72,fp,sp jbr L72 .data .text .align 1 .globl _mkpte _mkpte: .word L94 # # mkpte(flt_vadr) # long flt_vadr; # { long space, oldpte, pteno, regno; jbr L96 L97: # # space = (flt_vadr >> 30) & 0x3; shar $30,4(fp),r0 andl2 $3,r0 movl r0,-56(fp) # pteno = (flt_vadr >> PGSHIFT) & 0xfffff; shar $10,4(fp),r0 andl2 $1048575,r0 movl r0,-64(fp) # if (space==3) regno = SBR; /* System */ cmpl -56(fp),$3 jneq L98 clrl -68(fp) # if (space==2) { regno = P2BR; /* P2 */ L98: cmpl -56(fp),$2 jneq L99 movl $6,-68(fp) # pteno = LAST_VPGNO - 2; } movl $1048573,-64(fp) # if (space==1) regno = P1BR; /* P1 */ L99: cmpl -56(fp),$1 jneq L100 movl $4,-68(fp) # if (space==0) regno = P0BR; /* P0 */ L100: tstl -56(fp) jneq L101 movl $2,-68(fp) # # /* All access, V_BIT on */ # fixpv_pte(regno,pteno,&oldpte,PTE_KW | PTE_V); L101: pushl $-536870912 subl3 $60,fp,r0 pushl r0 pushl -64(fp) pushl -68(fp) callf $20,_fixpv_pte # # } ret .set L94,0x0 L96: subl3 $68,fp,sp jbr L97 .data .text .align 1 .globl _prot_handler _prot_handler: .word L104 # # prot_handler() # { jbr L106 L107: # asm(".align 2"); .align 2 # asm("handler1:"); handler1: # asm("movab _act_par0,_p_ptr"); /* Set pointer to fault parameters */ movab _act_par0,_p_ptr # asm("movl (sp)+,_act_par0"); movl (sp)+,_act_par0 # asm("movl (sp)+,_act_par1"); movl (sp)+,_act_par1 # asm("movl (sp)+,_act_par2"); movl (sp)+,_act_par2 # asm("movl (sp)+,_act_par3"); movl (sp)+,_act_par3 # asm("jmp *_ret_adr"); jmp *_ret_adr # } ret .set L104,0x0 L106: jbr L107 .data #

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