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Power 6/32 Unix version 1.2b

/*	mem.h	4.9	81/04/03	*/
/*	Tahoe version	Dec 1982	*/

/*
 * Memory controller registers
 *
 */


/*
 * Some bits definition for MCR
 */

#define	EED	0x01		/* Enable error detection */
#define	EEC	0x02		/* Enable error correction */
#define	WMD	0x04		/* Write memory diagnostic */
#define	RMD	0x08		/* Read memory diagnostic */
#define	INT	0x20		/* Init = power on bit */
#define	CEC	0x40		/* Clear error count */
#define	CME	0x80		/* Clear memory error */
#define	CMEC	0xff00		/* Corrected memory error count (mask) */

/*
 * MER bits
 */

#define	ERRCD	0x07		/* Error code (mask) */
#define    APE	1	/* Address parity error */
#define    DPE	2	/* Data parity error */
#define    DCE	3	/* Data check error */
#define    VTO	4	/* Versabus timeout */
#define    VBE	5	/* Versabus error */
#define    NEM	6	/* Non-existent memory */

#define	AXE	0x08		/* Adapter external error */
#define	ERM	0x10		/* Error master (0=CPU, 1=Versabus) */
#define	IVV	0x100		/* Illegal Versabus vector */

/*
 * MCBR bits
 */

#define	MCBR	0xffff0000
#define	MEAR	0xffff0000

/*
 * Frame for bus error
 */
struct buserframe {
	int	which_bus;		/* primary or secondary */
	int	memerreg;		/* memory error register */
	int	trp_pc;			/* trapped pc */
	int	trp_psl;		/* trapped psl */
};

extern long IOinit;

buserror(busef)
long *busef;
{
	register struct buserframe *frameptr;
	register long 	hardreg;

	if (IOinit) return;
	frameptr = (struct buserframe *)busef;
	writes("\nbus error at address : "); writeh(frameptr->trp_pc);
	writes(",  PSL : "); writeh(frameptr->trp_psl);
	hardreg =  frameptr->memerreg;

	writes("\nMEAR = "); writeh(((hardreg&MEAR)>>16)&0xffff);
	switch (hardreg & ERRCD){
		case (APE): 	writes("\tAddress parity error !! \n");
				break;
		case (DPE): 	writes("\tData parity error.\n");
				break;
		case (DCE):	writes("\tData check error.\n");
				break;
		case (VTO):	writes("\tVersabus timeout.\n");
				break;
		case (VBE):	writes("\tVersabus error !! \n");
				break;
		case (NEM):	writes("\tNon existent memory.\n");
				break;
		default:	writes("\tUnknown error code : ");
					writeh(hardreg&ERRCD);
	}
	if (hardreg&AXE) writes("\tAdapter external error\n");
	writes ("\tError master : ");
	if (hardreg&ERM) writes("Versabus\n");
		else writes ("Tahoe\n");
	if (hardreg&IVV) writes("\tIllegal interrupt vector\n");

	hardreg = frameptr->which_bus;
	writes("\nMCBR = "); writeh(((hardreg&0x1fff)>>16)&0xffff);
	writes("\tVersabus type : "); writeh(hardreg&0xffff); writec('\n');
}

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