![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to vddc.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / pits|
Return to vddc.h CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / pits |
1.1 root 1:
2: /*
3: * Definitions for VDDC CONTROLLER operations
4: *
5: */
6:
7: #define RETRY 200
8: #define DELAY(n) { register N = 3*(n); while (--N > 0 ); }
9:
10: /* *****************
11: Device parameters
12: *****************
13: */
14:
15: #define UDC_BLKLEN 256 /* Block length on UDC */
16: #define SECTSIZ 256 /* sector size */
17: #define BLKSIZ 1024 /* Logical block size */
18:
19: struct DEVPAR {
20: long nocyl; /* No of cylinders */
21: long nohead; /* No of heads */
22: long notraks; /* No of data surfaces/cyl */
23: long secs_trak; /* No of sectors/track */
24: long sector_siz; /* Sector size */
25: char alive;
26: char name[5];
27: };
28:
29: struct DA {
30: long devaddr; /* device address of controller */
31: long intvect; /* interrupt vector */
32: char online; /* online flag */
33: };
34:
35:
36: /* **********************
37: VDDC packet structures
38: **********************
39: */
40:
41: struct MDCB { /* Master DCB : 4 longwords */
42: long fdcb_adr; /* 1st DCB address */
43: long dcb_active;/* address of DCB in progress */
44: long dcb_int; /* address of DCB causing interrupt */
45: long ctlr_stat; /* Controller status */
46: };
47:
48: struct DCB { /* DCB structure */
49: long nxt_dcb; /* Address of next DCB */
50: unsigned short int_flags; /* Interrupt,chain flags */
51: unsigned short opcode; /* opcode */
52: long dcb_stat; /* operation status */
53: unsigned short unused;
54: char dev_sel; /* Device select */
55: char trail_wcnt; /* Trailer word count */
56:
57: long err_memadr; /* These following fields are not */
58: unsigned short unused1; /* defined in the Manual. */
59: unsigned short err_wcount;
60: unsigned short err_track;
61: unsigned short err_cyl; /* Up to here !! */
62:
63: long trailer[255]; /* Trailer 0-256 longwords */
64: };
65:
66:
67: /*
68: ** DCB Command Codes
69: */
70:
71: #define RD_DATA 0x80 /* Read Data */
72: #define FTR 0xc0 /* Full Track Read */
73: #define RAS 0x90 /* Read and Scatter */
74: #define C 0xa0 /* Compare */
75: #define FTC 0xe0 /* Full Track Compare */
76: #define RHDE 0x180 /* Read Header, Data & ECC (not used) */
77: #define WD 0x00 /* Write Data */
78: #define FTW 0x40 /* Full Track Write */
79: #define WR_COMP 0x20 /* Write Then Compare */
80: #define FTWTC 0x60 /* Full Track Write Then Compare */
81: #define GAW 0x10 /* Gather and Write */
82: #define WDE 0x100 /* Write Data & ECC (not used) */
83: #define FORMAT 0x900 /* Format Sector */
84: #define GWC 0x30 /* Gather Write & Compare */
85: #define START_DR 0x800 /* Start drives */
86: #define STOP_DR 0xa00 /* Stop drives */
87: #define SEEK 0xb00 /* Seek */
88: #define INITIALIZE 0xc00 /* Initialize VDDC */
89: #define DIAGNOSE 0xd00 /* Diagnose (self-test) VDDC */
90: #define CONFIG 0xe00 /* Reset/Configure VDDC/DDI/Drive(s) */
91: #define STATUS 0xf00 /* VDDC Status */
92: /*
93: *************************
94: VDDC CONTROLLER PARAMETERS
95: *************************
96: */
97: #define IOBASE 0xff000000
98: /* DCB longword no. 1 */
99:
100: #define NO_CHAIN 0
101:
102: /* DCB longword no. 2 */
103:
104: #define NOOP 0 /* No-op */
105: #define NO_MODIFIER 0x0 /* No modifier */
106: #define SGATHER 0x100 /* Scatter gather */
107: #define COMPARE 0x200 /* Compare */
108: #define NO_INT 0 /* No interrupt */
109: #define INT_DONE 1 /* Interrupt when done */
110: #define INT_ERROR 2 /* Interrupt on error */
111: #define INT_SUCCESS 3 /* Interrupt on success */
112:
113: /* DCB longword no. 3 */
114:
115: #define HARDERR_MASK 0xffffffff /* Hard error mask */
116: #define SOFTERR_MASK 0xffffffff /* Soft error mask */
117: #define DATA_CORRECT 0x100000 /* Controller performed data correct */
118: #define HARD_ERROR 0x200000 /* Hard error */
119: #define SOFT_ERROR 0x400000 /* Soft error (retry successful) */
120: #define ANY_ERROR 0x800000 /* Any error : bits 20,21,22 set */
121: #define DCB_ABORT 0x10000000 /* DCB aborted */
122: #define UNSUCCESS 0x20000000 /* Unsuccessful completion */
123: #define DCB_DONE 0x40000000 /* DCB completed */
124: #define DCB_STARTED 0x80000000
125: #define INVL_CMD writes("\ninvalid command\n")
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.