![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to poc_er_codes CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d|
Return to poc_er_codes CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d |
1.1 root 1: #poc1
2: 1 Zero flag was not set DL,CT
3: 2 Negative flag was not set DL,CT
4: 3 Negative flag stayed set DL,CT
5: 4 Carry flag was not set DL,CT
6: 5 Carry flag stayed set DL,CT
7: 6 Compare error; LIT does not contain
8: all zeroes DL,CT
9: 7 Compare error; LIT does not contain
10: the value -1 DL,CT
11: 8 Compare error; bit 0 is not set in
12: LIT DL,CT
13: 9 Compare error; bit 1 is not set in
14: LIT DL,CT
15: a Compare error; bit 2 is not set in
16: LIT DL,CT
17: b Compare error; bit 3 is not set in
18: LIT DL,CT
19: c Compare error; bit 4 is not set in
20: LIT DL,CT
21: d Compare error; bit 5 is not set in
22: LIT DL,CT
23: e Compare error; bit 6 is not set in
24: LIT DL,CT
25: f Compare error; bit 7 is not set in
26: LIT DL,CT
27: 10 Compare error; bit 8 is not set in
28: LIT DL,CT
29: 11 Compare error; bit 9 is not set in
30: LIT DL,CT
31: 12 Compare error; bit 10 is not set in
32: LIT DL,CT
33: 13 Compare error; bit 11 is not set in
34: LIT DL,CT
35: 14 Compare error; bit 12 is not set in
36: LIT DL,CT
37: 15 Compare error; bit 13 is not set in
38: LIT DL,CT
39: 16 Compare error; bit 14 is not set in
40: LIT DL,CT
41: 17 Compare error; bit 15 is not set in
42: LIT DL,CT
43: 18 Compare error; bit 16 is not set in
44: LIT DL,CT
45: 19 Compare error; bit 17 is not set in
46: LIT DL,CT
47: 1a Compare error; bit 18 is not set in
48: LIT DL,CT
49: 1b Compare error; bit 19 is not set in
50: LIT DL,CT
51: 1c Compare error; bit 20 is not set in
52: LIT DL,CT
53: 1d Compare error; bit 21 is not set in
54: LIT DL,CT
55: 1e Compare error; bit 22 is not set in
56: LIT DL,CT
57: 1f Compare error; bit 23 is not set in
58: LIT DL,CT
59: 20 Compare error; bit 24 is not set in
60: LIT DL,CT
61: 21 Compare error; bit 25 is not set in
62: LIT DL,CT
63: 22 Compare error; bit 26 is not set in
64: LIT DL,CT
65: 23 Compare error; bit 27 is not set in
66: LIT DL,CT
67: 24 Compare error; bit 28 is not set in
68: LIT DL,CT
69: 25 Compare error; bit 29 is not set in
70: LIT DL,CT
71: 26 Compare error; bit 30 is not set in
72: LIT DL,CT
73: 27 Compare error; bit 31 is not set in
74: LIT DL,CT
75: 28 Compare error. a pattern of
76: AAAAAAAA is placed into LIT and
77: sotred in a temporary location.
78: Then, a pattern of 55555555 is moved
79: into LIT. The test ORs the data in
80: the temporary location with the
81: contents of LIT. The result should
82: be FFFFFFFF, but the OR yields a
83: different value. DL,CT
84: 29 Compare error; LIT should have
85: contained aaaaaaaa DL,CT
86: 2a DL bus compare error. The test
87: transferred 55555555 from the DL
88: bus to the LIT. When read,
89: however, the LIT did not
90: contain the eight 5 characters. DL,CT
91: 2b DL bus compare error. The test
92: transferred aaaaaaaa from the DL
93: bus to the LIT. When read,
94: however, the LIT did not
95: contain the eight a characters. DL,CT
96: 2c DL bus compare error. The test
97: transferred 3c3c3c3c from the DL
98: bus to the LIT. When read,
99: however, the LIT did not contain
100: the four sets of 3c
101: characters. DL,CT
102: 2d DL bus compare error. The test
103: placed c3c3c3c3 on the DL bus.
104: When read, however, LIT did not
105: contain the four sets of c3
106: characters. DL,CT
107: 2e CD bus compare error; expected zero DL,AG,AT
108: 2f CD bus compare error; expected bit
109: zero to be set DL,MEM
110: 30 CD bus compare error; expected bit 1
111: to be set DL,MEM
112: 31 CD bus compare error; expected bit 2
113: to be set DL,MEM
114: 32 CD bus compare error; expected bit 3
115: to be set DL,MEM
116: 33 CD bus compare error; expected bit 4
117: to be set DL,MEM
118: 34 CD bus compare error; expected bit 5
119: to be set DL,MEM
120: 35 CD bus compare error; expected bit 6
121: to be set DL,MEM
122: 36 CD bus compare error; expected bit 7
123: to be set DL,MEM
124: 37 CD bus compare error; expected bit 8
125: to be set DL,MEM
126: 38 CD bus compare error; expected bit 9
127: to be set DL,MEM
128: 39 CD bus compare error; expected bit 10
129: to be set DL,MEM
130: 3a CD bus compare error; expected bit 11
131: to be set DL,MEM
132: 3b CD bus compare error; expected bit 12
133: to be set DL,MEM
134: 3c CD bus compare error; expected bit 13
135: to be set DL,MEM
136: 3d CD bus compare error; expected bit 14
137: to be set DL,MEM
138: 3e CD bus compare error; expected bit 15
139: to be set DL,MEM
140: 3f CD bus compare error; expected bit 16
141: to be set DL,MEM
142: 40 CD bus compare error; expected bit 17
143: to be set DL,MEM
144: 41 CD bus compare error; expected bit 18
145: to be set DL,MEM
146: 42 CD bus compare error; expected bit 19
147: to be set DL,MEM
148: 43 CD bus compare error; expected bit 20
149: to be set DL,MEM
150: 44 CD bus compare error; expected bit 21
151: to be set DL,MEM
152: 45 CD bus compare error; expected bit 22
153: to be set DL,MEM
154: 46 CD bus compare error; expected bit 23
155: to be set DL,MEM
156: 47 CD bus compare error; expected bit 24
157: to be set DL,MEM
158: 48 CD bus compare error; expected bit 25
159: to be set DL,MEM
160: 49 CD bus compare error; expected bit 26
161: to be set DL,MEM
162: 4a CD bus compare error; expected bit 27
163: to be set DL,MEM
164: 4b CD bus compare error; expected bit 28
165: to be set DL,MEM
166: 4c CD bus compare error; expected bit 29
167: to be set DL,MEM
168: 4d CD bus compare error; expected bit 30
169: to be set DL,MEM
170: 4e CD bus compare error; expected bit 31
171: to be set DL,MEM
172: 4f CD bus compare error with general-purpose
173: registers DL,CT
174: 50 Left shift (RAM) with zeroes failed DL,CT
175: 51 Right shift (RAM) with zeroes failed DL,CT
176: 52 Left shift (RAM) with ones failed DL,CT
177: 53 Right shift (RAM) with ones failed DL,CT
178: 54 The test shifted the Q register and a
179: general-purpose register to the left
180: using LSFTL. The shift failed. DL,CT
181: 55 The test shifted the Q register and a
182: general-purpose register to the right
183: using LSFTR. The shift failed. DL,CT
184: 56 Contents of register R0 incorrect; should
185: be equal to 1. DL,CT
186: 57 Contents of register R1 incorrect; should
187: be equal to 2. DL,CT
188: 58 Contents of register R2 incorrect; should
189: be equal to 3. DL,CT
190: 59 Contents of register R3 incorrect; should
191: be equal to 4. DL,CT
192: 5a Contents of register R4 incorrect; should
193: be equal to 5. DL,CT
194: 5b Contents of register R5 incorrect; should
195: be equal to 6. DL,CT
196: 5c Contents of register R6 incorrect; should
197: be equal to 7. DL,CT
198: 5d Contents of register R7 incorrect; should
199: be equal to 8. DL,CT
200: 5e Contents of register R8 incorrect; should
201: be equal to 9. DL,CT
202: 5f Contents of register R9 incorrect; should
203: be equal to A. DL,CT
204: 60 Contents of register R10 incorrect; should
205: be equal to B. DL,CT
206: 61 Contents of register R11 incorrect; should
207: be equal to C. DL,CT
208: 62 Contents of register R12 incorrect; should
209: be equal to D. DL,CT
210: 63 Contents of register R13 incorrect; should
211: be equal to E. DL,CT
212: 64 Contents of register R14 incorrect; should
213: be equal to F. DL,CT
214: 65 Contents of register R15 incorrect; should
215: be equal to 10. DL,CT
216: 66 Register alternating pattern test failed. DL,CT
217: 67 Data loop word swap function failed. DL,CT
218: 68 Sign-extended (with 1s) word mode failed.
219: This tests the ms-word. DL,CT,MEM
220: 69 Sign-extended (with 0s) word mode failed.
221: This tests the ms-word. DL,CT,MEM
222: 6a Zero-extended (with 1s) word mode failed.
223: This tests the ms-word.
224: 6b Sign-extended (with 1s) byte mode failed. DL,CT,MEM
225: 6c Sign-extended (with 0s) byte mode failed. DL,CT,MEM
226: 6d Zero-extended (with 1s) byte mode failed. DL,CT,MEM
227: 6e Switch register test failed. CT,DL
228: 6f Zero flag stayed set. DL,CT
229: 70 The test independently shifted the Q
230: register and a gp register to the left
231: using SFTBL0. The shift failed. DL,CT
232: 71 The test independently shifted the Q
233: register and a gp register to the
234: right using SFTBR0. The shift failed. DL,CT
235: 72 Zero-extend word mode, transferring
236: data from memory to memory failed. DL,CT,MEM
237: 73 Zero-extend byte mode, tranferring
238: data from memory to memory failed. DL,CT,MEM
239: 74 Sign-extended (with 1s) word mode failed.
240: This tests the 1s-word. DL,CT,MEM
241: 75 Sign-extended (with 0s) word mode failed.
242: This tests the 1s-word. DL,CT,MEM
243: 7A Unique address error. The test
244: wrote an address to the CA
245: register. It then compared the
246: original address with the address
247: in the register, and the addresses
248: were different. AG,AT
249: 7B Unique address error. The test
250: stored the same address in both
251: the CA register and another
252: location. The address in the CA
253: should have pointed to the second
254: location. The value in the CA,
255: however, was incorrect and
256: differed from the value in the
257: second location. MEM,AT
258: 7C Complement unique address data error MEM,AT
259: 7D Memory data compare error. The
260: routine wrote some data to
261: location 0x4. It then read 0x4
262: and found that the data was
263: inaccurate. MEM,AT
264: 7E Memory data compare error; expected
265: all zeroes MEM,AT
266: 7F Memory data compare error; expected
267: all ones MEM,AT
268: 80 Incorrect cache address; CA was not
269: equal to 1 AG,CT,AT
270: 81 Incorrect cache address; CA was not
271: equal to 2 AG,AT
272: 82 Incorrect cache address; CA was not
273: equal to 3 AG,AT
274: 83 Incorrect cache address; CA was not
275: equal to 4 AG,AT
276: 84 Incorrect cache address; CA was not
277: equal to 5 AG,AT
278: 85 Incorrect cache address; CA was not
279: equal to 6 AG,AT
280: 86 Incorrect cache address; CA was not
281: equal to 7 AG,AT
282: 87 Incorrect cache address; CA was not
283: equal to 8 AG,AT
284: 88 Incorrect cache address; CA was not
285: equal to 9 AG,AT
286: 89 Incorrect cache address; CA was not
287: equal to a AG,AT
288: 8a Incorrect cache address; CA was not
289: equal to b AG,AT
290: 8b Incorrect cache address; CA was not
291: equal to c AG,AT
292: 8c Incorrect cache address; CA was not
293: equal to d AG,AT
294: 8d Incorrect cache address; CA was not
295: equal to e AG,AT
296: 8e Incorrect cache address; CA was not
297: equal to f AG,AT
298: 8f Incorrect cache address; CA was not
299: equal to 10 AG,AT
300: 90 AC was changed following sameac.
301: The test used a particular address
302: with an instruction and wrote that
303: address to the address control
304: (AC) area. It also stored the
305: address in a temporary location.
306: After executing sameac, the
307: routine expected to find the same
308: address in the AC that it found in
309: the temporary location. The two
310: addresses, however, were not the
311: same. CT,AG
312: 91 AC was changed following sameacp.
313: This error is similar to error
314: number 0x90. The routine used the
315: same method to check the sameacp
316: function. (In addition to the
317: operations performed by sameac,
318: the sameacp function preserves the
319: addressing mode of the instruction
320: and turns on a bit that indicates
321: use of a physical address.) AT,AG
322: 92 AC was changed following sameac.
323: See the description of error 0x90. CT,AG
324: 93 AC was changed following sameacp.
325: See the description of error 0x91. CT,AG
326: 94 Original CA was destroyed after a
327: translation buffer operation (Tbop). AG,CT
328: 95 Incorrect data was in the stack
329: pointer following a data-loop-to-
330: SP (dl2sp) function. AG,CT
331: 96 After executing the last-stack-
332: pointer-to-CA-register (lsp2ca)
333: function, the test found incorrect
334: data in the location that stored
335: the last stack pointer. AG,CT
336: 97 Incorrect data was in the system base
337: register (SBR). AG,CT
338: 98 Incorrect data was in the P0 space
339: base register (P0BR). AG,CT
340: 99 Incorrect data was in the P1 space
341: base register (P1BR). AG,CT
342: 9a Incorrect data was in the P2 space
343: base register (P2BR). AG,CT
344: 9b Incorrect data was in the system length
345: register (SLR). AG,CT
346: 9c Incorrect data was in the P0 space
347: length register (P0LR). AG,CT
348: 9d Incorrect data was in the P1 space
349: length register (P1LR). AG,CT
350: 9e After decrementing the address stored
351: in r0, the test found that the
352: resulting address was incorrect. AG,CT
353: 9f After decrementing the address stored
354: in r2, the test found that the
355: resulting address was incorrect. AG,CT
356: a0 After decrementing the address stored
357: in r4, the test found that the
358: resulting address was incorrect. AG,CT
359: a1 After decrementing the address stored
360: in r8, the test found that the
361: resulting address was incorrect. AG,CT
362: a2 After decrementing the address stored
363: in r15, the test found that the
364: resulting address was incorrect. AG,CT
365: a3 After adding the contents of r0 to
366: a displacement (displ), the test
367: found that the resulting offset
368: was incorrect. AG,CT
369: a4 After adding the contents of r2 to
370: a displacement (displ), the test
371: found that the resulting offset
372: was incorrect. AG,CT
373: a5 After adding the contents of r4 to
374: a displacement (displ), the test
375: found that the resulting offset
376: was incorrect. AG,CT
377: a6 After adding the contents of r8 to
378: a displacement (displ), the test
379: found that the resulting offset
380: was incorrect. AG,CT
381: a7 After adding the contents of r15 to
382: a displacement (displ), the test
383: found that the resulting offset
384: was incorrect. AG,CT
385: a8 The test generated an address based
386: on the value in the LIT register
387: (absrel). The resulting address,
388: however, was incorrect. AG,CT
389: a9 After decrementing the contents of
390: the CA register (decra), the
391: routine read and detected an
392: incorrect address. AG,CT
393: aa After incrementing the contents of
394: the CA register (incra), the
395: routine read and detected an
396: incorrect address. AG,CT
397: ab Error when controlling L bus (alit) AG,CT
398: ac The alit function changed the value in
399: the CA register. AG,CT
400: ad Incorrect results after a pop AG,CT
401: ae Incorrect results after a push AG,CT
402: af After adding the contents of the
403: stack pointer to an offset, the
404: test obtained an incorrect value. AG,CT
405: b0 Incorrect results after subtest E
406: (lpushl) AG,CT
407: b1 Incorrect results after subtest F
408: (pusha) AG,CT
409: b2 Incorrect data from P2LR AG,CT
410: b3 Incorrect CA following a push AG,AT
411: b4 Incorrect SP following a push AG,AT
412: b5 Incorrect SP following a pop AG,AT
413: b6 Incorrect CA; 0+0 != 0 AG,AT
414: b7 Incorrect CA; -1 + (-1) != -2 AG,AT
415: b8 Incorrect CA; -1 + 1 != 0 AG,AT
416: b9 Incorrect CA; 1 + (-1) != 0 AG,AT
417: ba Incorrect CA; As + 5s != -1 AG,AT
418: bb Incorrect CA; 5s + As != -1 AG,AT
419: bc Incorrect cache address; CA != ~1 AG,AT
420: bd Incorrect cache address; CA != ~2 AG,AT
421: be Incorrect cache address; CA != ~3 AG,AT
422: bf Incorrect cache address; CA != ~4 AG,AT
423: c0 A miss did not occur in data cache AT,AG
424: r3 Contents of cell after purge
425: r4 Address
426: r8 Data cache key
427: r13 Subtest number = 1
428: c1 A hit did not occur in data cache AT,AG
429: r10 Address
430: r13 Subtest number = 2
431: c2 A miss did not occur in data cache AT,AG
432: r4 Data bit used by scanner
433: r5 Data bit used for testing
434: r7 Scan address
435: r10 Address
436: r11 Index of element
437: r13 Subtest number = 2
438: c3 A hit did not occur in data cache AT,AG
439: r8 Current data cache key
440: r10 Address
441: r13 Subtest number = 2
442: c4 A hit did not occur in data cache AT,AG
443: r10 Address
444: r13 Subtest number = 2
445: c5 A hit did not occur in data cache AT,AG
446: r10 Address
447: r13 Subtest number = 2
448: c6 Incorrect cache data word following a
449: write hit DL,AT
450: r2 Address
451: r5 Actual data
452: r10 Expected data
453: r13 Subtest number = 3
454: c7 Incorrect cache data word following a
455: unique write hit DL,AT
456: r2 Address
457: r5 Actual data
458: r10 Expected data
459: r13 Subtest number = 3
460: c8 A miss did not occur in the translation
461: buffer AT,AG
462: r2 Address
463: r13 Subtest number = 4
464: c9 A miss did not occur in the translation
465: buffer AT,AG
466: r2 Address
467: r13 Subtest number = 4
468: ca A miss did not occur in the translation
469: buffer AT,AG
470: r2 Address
471: r13 Subtest number = 4
472: cb A miss did not occur in the translation
473: buffer AT,AG
474: r2 Address
475: r13 Subtest number = 4
476: cc A hit did not occur in the translation
477: buffer AT,AG
478: r2 Address
479: r13 Subtest number = 5
480: cd A hit did not occur in the translation
481: buffer AT,AG
482: r2 Address
483: r13 Subtest number = 5
484: ce A hit did not occur in the translation
485: buffer AT,AG
486: r2 Address
487: r3 Tested data bit
488: r13 Subtest number = 5
489: Q Tested space (P0, P1, P2, or system)
490: cf A hit did not occur in the translation
491: buffer AT,AG
492: r2 Address
493: r9 Translation buffer key
494: r13 Subtest number = 5
495: d0 Compare error for write hit of page
496: table entry AT,MEM
497: r2 Address
498: r7 Actual data
499: r10 Expected data
500: r13 Subtest number = 6
501: d1 Incorrect cache address; CA != ~5 AG,AT
502: d2 Incorrect cache address; CA != ~6 AG,AT
503: d3 Incorrect cache address; CA != ~7 AG,AT
504: d4 Incorrect cache address; CA != ~8 AG,AT
505: d5 Incorrect cache address; CA != ~9 AG,AT
506: d6 Incorrect cache address; CA != ~A AG,AT
507: d7 Incorrect cache address; CA != ~B AG,AT
508: d8 Incorrect cache address; CA != ~C AG,AT
509: d9 Incorrect cache address; CA != ~D AG,AT
510: da Incorrect cache address; CA != ~E AG,AT
511: db Incorrect cache address; CA != ~F AG,AT
512: dc Incorrect cache address; CA != ~10 AG,AT
513: df Incorrect operand address; 0def0000
514: plus ffff IP,DL
515: e0 Data compare error in IP registers;
516: expected all ones IP,CT
517: e1 Data compare error in IP registers;
518: walking ones test IP,CT
519: e2 Data compare error in IP registers;
520: walking zeroes test IP,CT
521: e3 Instruction address counter error IP,CT
522: e4 Instruction fetch error LIA incorrect IP,CT
523: e5 Incorrect PC after instruction fetch IP,CT
524: e6 Unable to set macro Z flag DL,CT
525: e7 Unable to set macro N flag DL,CT
526: e8 Unable to set macro C flag DL,CT
527: e9 Unable to set macro V flag DL,CT
528: ea Incorrect PC following a branch.
529: With Z set, the test should have
530: branched to a particular location. IP,CT
531: eb Incorrect PC following a branch.
532: With Z clear, the test should have
533: branched to a particular location. IP,CT
534: ec Incorrect PC following a branch.
535: With N set, the test should have
536: branched to a particular location. IP,CT
537: ed Incorrect PC following a branch.
538: With N clear, the test should have
539: branched to a particular location. IP,CT
540: ee Wrong literal (zero-extend byte) IP,DL
541: ef Wrong PC (zero-extend byte) IP,DL
542: f0 Wrong literal (sign-extend byte) IP,DL
543: f1 Wrong PC (sign-extend byte) IP,DL
544: f2 Wrong literal (zero-extend word) IP,DL
545: f3 Wrong PC (zero-extend word) IP,DL
546: f4 Wrong literal (sign-extend word) IP,DL
547: f5 Wrong PC (sign-extend word) IP,DL
548: f6 Wrong literal (zero-extend longword) IP,DL
549: f7 Wrong PC (zero-extend longword) IP,DL
550: f8 Wrong literal (sign-extend longword) IP,DL
551: f9 Wrong PC (sign-extend longword) IP,DL
552: fa Wrong literal of aaaaaaaa IP,DL
553: fb Wrong PC (move lit of aaaaaaaa) IP,DL
554: fc Wrong literal of 33333333 IP,DL
555: fd Wrong PC (move lit of 33333333) IP,DL
556: fe Incorrect operand address; 0def0000
557: plus 0000 IP,DL
558: #poc2
559: 01 Failed decode of halt instruction IP,CT
560: 02 Failed decode of nop instruction IP,CT
561: 03 Failed decode of rei instruction IP,CT
562: 04 Failed decode of movblk instruction IP,CT
563: 05 Failed decode of movl instruction;
564: movl r0 to r5 IP,CT
565: 06 Failed decode of movl instruction;
566: movl r5 to r0 IP,CT
567: 07 Failed decode of movl instruction;
568: movl ra to r5 IP,CT
569: 08 Failed decode of movl instruction;
570: movl r5 to ra IP,CT
571: 09 Failed decode of movl instruction;
572: movl byte literal to r5 IP,CT
573: 0a Failed decode of movl instruction;
574: movl byte literal to ra IP,CT
575: 0b Failed decode of movl instruction;
576: movl word literal to r5 IP,CT
577: 0c Failed decode of movl instruction;
578: movl word literal to ra IP,CT
579: 0d Failed decode of movl instruction;
580: movl longword literal to r5 IP,CT
581: 0e Failed decode of movl instruction;
582: movl longword literal to ra IP,CT
583: 0f Failed decode of ret instruction IP,CT
584: 10 Failed decode of clrb instruction IP,CT
585: 11 Failed decode of clrw instruction IP,CT
586: 12 Failed decode of clrl instruction IP,CT
587: 13 Failed decode of push instruction IP,CT
588: 14 Failed decode of add3 instruction IP,CT
589: 15 Failed decode of call instruction;
590: stack pointer incorrect CT,IP
591: 16 Failed decode of call instruction;
592: r0 not saved properly CT,IP
593: 17 Failed decode of call instruction;
594: r1 not saved properly CT,IP
595: 18 Failed decode of call instruction;
596: r2 not saved properly CT,IP
597: 19 Failed decode of call instruction;
598: r3 not saved properly CT,IP
599: 1a Failed decode of call instruction;
600: r4 not saved properly CT,IP
601: 1b Failed decode of call instruction;
602: r5 not saved properly CT,IP
603: 1c Failed decode of call instruction;
604: r6 not saved properly CT,IP
605: 1d Failed decode of call instruction;
606: r7 not saved properly CT,IP
607: 1e Failed decode of call instruction;
608: r8 not saved properly CT,IP
609: 1f Failed decode of call instruction;
610: r9 not saved properly CT,IP
611: 20 Failed decode of call instruction;
612: ra not saved properly CT,IP
613: 21 Failed decode of call instruction;
614: rb not saved properly CT,IP
615: 22 Failed decode of call instruction;
616: rc not saved properly CT,IP
617: 23 Failed decode of call instruction;
618: return address not saved properly CT,IP
619: 24 Failed decode of call instruction;
620: mask + reg save not saved properly CT,IP
621: 25 Failed decode of call instruction;
622: reg d not saved properly CT,IP
623: 26 Failed decode of movl instruction;
624: movl r5 to cache (auto decr SP) IP,CT
625: 27 Failed decode of movl instruction;
626: movl cache (auto incr SP) to r5 IP,CT
627: 28 Failed decode of movl instruction;
628: movl cache (auto incr deferred) to SP IP,CT
629: 29 Failed decode of movl instruction;
630: movl cache (r5 deferred) to r4 IP,CT
631: 2a Failed decode of movl instruction;
632: movb cache (r5 + byte) to r4 IP,CT
633: 2b Failed decode of movl instruction;
634: movw cache (r5 + word) to r4 IP,CT
635: 2c Failed decode of movl instruction;
636: movl cache (r5 + longword) to r4 IP,CT
637: 2d Failed decode of movl instruction;
638: movl index by r5 to r4 AG,IP
639: 2e Failed decode of movl instruction;
640: movw index by r5 to r4 AG,IP
641: 2f Failed decode of movl instruction;
642: movb index by r5 to r4 AG,IP
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.