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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d|
Return to poc_er_codes CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d |
Power 6/32 Unix version 1.2b
#poc1
1 Zero flag was not set DL,CT
2 Negative flag was not set DL,CT
3 Negative flag stayed set DL,CT
4 Carry flag was not set DL,CT
5 Carry flag stayed set DL,CT
6 Compare error; LIT does not contain
all zeroes DL,CT
7 Compare error; LIT does not contain
the value -1 DL,CT
8 Compare error; bit 0 is not set in
LIT DL,CT
9 Compare error; bit 1 is not set in
LIT DL,CT
a Compare error; bit 2 is not set in
LIT DL,CT
b Compare error; bit 3 is not set in
LIT DL,CT
c Compare error; bit 4 is not set in
LIT DL,CT
d Compare error; bit 5 is not set in
LIT DL,CT
e Compare error; bit 6 is not set in
LIT DL,CT
f Compare error; bit 7 is not set in
LIT DL,CT
10 Compare error; bit 8 is not set in
LIT DL,CT
11 Compare error; bit 9 is not set in
LIT DL,CT
12 Compare error; bit 10 is not set in
LIT DL,CT
13 Compare error; bit 11 is not set in
LIT DL,CT
14 Compare error; bit 12 is not set in
LIT DL,CT
15 Compare error; bit 13 is not set in
LIT DL,CT
16 Compare error; bit 14 is not set in
LIT DL,CT
17 Compare error; bit 15 is not set in
LIT DL,CT
18 Compare error; bit 16 is not set in
LIT DL,CT
19 Compare error; bit 17 is not set in
LIT DL,CT
1a Compare error; bit 18 is not set in
LIT DL,CT
1b Compare error; bit 19 is not set in
LIT DL,CT
1c Compare error; bit 20 is not set in
LIT DL,CT
1d Compare error; bit 21 is not set in
LIT DL,CT
1e Compare error; bit 22 is not set in
LIT DL,CT
1f Compare error; bit 23 is not set in
LIT DL,CT
20 Compare error; bit 24 is not set in
LIT DL,CT
21 Compare error; bit 25 is not set in
LIT DL,CT
22 Compare error; bit 26 is not set in
LIT DL,CT
23 Compare error; bit 27 is not set in
LIT DL,CT
24 Compare error; bit 28 is not set in
LIT DL,CT
25 Compare error; bit 29 is not set in
LIT DL,CT
26 Compare error; bit 30 is not set in
LIT DL,CT
27 Compare error; bit 31 is not set in
LIT DL,CT
28 Compare error. a pattern of
AAAAAAAA is placed into LIT and
sotred in a temporary location.
Then, a pattern of 55555555 is moved
into LIT. The test ORs the data in
the temporary location with the
contents of LIT. The result should
be FFFFFFFF, but the OR yields a
different value. DL,CT
29 Compare error; LIT should have
contained aaaaaaaa DL,CT
2a DL bus compare error. The test
transferred 55555555 from the DL
bus to the LIT. When read,
however, the LIT did not
contain the eight 5 characters. DL,CT
2b DL bus compare error. The test
transferred aaaaaaaa from the DL
bus to the LIT. When read,
however, the LIT did not
contain the eight a characters. DL,CT
2c DL bus compare error. The test
transferred 3c3c3c3c from the DL
bus to the LIT. When read,
however, the LIT did not contain
the four sets of 3c
characters. DL,CT
2d DL bus compare error. The test
placed c3c3c3c3 on the DL bus.
When read, however, LIT did not
contain the four sets of c3
characters. DL,CT
2e CD bus compare error; expected zero DL,AG,AT
2f CD bus compare error; expected bit
zero to be set DL,MEM
30 CD bus compare error; expected bit 1
to be set DL,MEM
31 CD bus compare error; expected bit 2
to be set DL,MEM
32 CD bus compare error; expected bit 3
to be set DL,MEM
33 CD bus compare error; expected bit 4
to be set DL,MEM
34 CD bus compare error; expected bit 5
to be set DL,MEM
35 CD bus compare error; expected bit 6
to be set DL,MEM
36 CD bus compare error; expected bit 7
to be set DL,MEM
37 CD bus compare error; expected bit 8
to be set DL,MEM
38 CD bus compare error; expected bit 9
to be set DL,MEM
39 CD bus compare error; expected bit 10
to be set DL,MEM
3a CD bus compare error; expected bit 11
to be set DL,MEM
3b CD bus compare error; expected bit 12
to be set DL,MEM
3c CD bus compare error; expected bit 13
to be set DL,MEM
3d CD bus compare error; expected bit 14
to be set DL,MEM
3e CD bus compare error; expected bit 15
to be set DL,MEM
3f CD bus compare error; expected bit 16
to be set DL,MEM
40 CD bus compare error; expected bit 17
to be set DL,MEM
41 CD bus compare error; expected bit 18
to be set DL,MEM
42 CD bus compare error; expected bit 19
to be set DL,MEM
43 CD bus compare error; expected bit 20
to be set DL,MEM
44 CD bus compare error; expected bit 21
to be set DL,MEM
45 CD bus compare error; expected bit 22
to be set DL,MEM
46 CD bus compare error; expected bit 23
to be set DL,MEM
47 CD bus compare error; expected bit 24
to be set DL,MEM
48 CD bus compare error; expected bit 25
to be set DL,MEM
49 CD bus compare error; expected bit 26
to be set DL,MEM
4a CD bus compare error; expected bit 27
to be set DL,MEM
4b CD bus compare error; expected bit 28
to be set DL,MEM
4c CD bus compare error; expected bit 29
to be set DL,MEM
4d CD bus compare error; expected bit 30
to be set DL,MEM
4e CD bus compare error; expected bit 31
to be set DL,MEM
4f CD bus compare error with general-purpose
registers DL,CT
50 Left shift (RAM) with zeroes failed DL,CT
51 Right shift (RAM) with zeroes failed DL,CT
52 Left shift (RAM) with ones failed DL,CT
53 Right shift (RAM) with ones failed DL,CT
54 The test shifted the Q register and a
general-purpose register to the left
using LSFTL. The shift failed. DL,CT
55 The test shifted the Q register and a
general-purpose register to the right
using LSFTR. The shift failed. DL,CT
56 Contents of register R0 incorrect; should
be equal to 1. DL,CT
57 Contents of register R1 incorrect; should
be equal to 2. DL,CT
58 Contents of register R2 incorrect; should
be equal to 3. DL,CT
59 Contents of register R3 incorrect; should
be equal to 4. DL,CT
5a Contents of register R4 incorrect; should
be equal to 5. DL,CT
5b Contents of register R5 incorrect; should
be equal to 6. DL,CT
5c Contents of register R6 incorrect; should
be equal to 7. DL,CT
5d Contents of register R7 incorrect; should
be equal to 8. DL,CT
5e Contents of register R8 incorrect; should
be equal to 9. DL,CT
5f Contents of register R9 incorrect; should
be equal to A. DL,CT
60 Contents of register R10 incorrect; should
be equal to B. DL,CT
61 Contents of register R11 incorrect; should
be equal to C. DL,CT
62 Contents of register R12 incorrect; should
be equal to D. DL,CT
63 Contents of register R13 incorrect; should
be equal to E. DL,CT
64 Contents of register R14 incorrect; should
be equal to F. DL,CT
65 Contents of register R15 incorrect; should
be equal to 10. DL,CT
66 Register alternating pattern test failed. DL,CT
67 Data loop word swap function failed. DL,CT
68 Sign-extended (with 1s) word mode failed.
This tests the ms-word. DL,CT,MEM
69 Sign-extended (with 0s) word mode failed.
This tests the ms-word. DL,CT,MEM
6a Zero-extended (with 1s) word mode failed.
This tests the ms-word.
6b Sign-extended (with 1s) byte mode failed. DL,CT,MEM
6c Sign-extended (with 0s) byte mode failed. DL,CT,MEM
6d Zero-extended (with 1s) byte mode failed. DL,CT,MEM
6e Switch register test failed. CT,DL
6f Zero flag stayed set. DL,CT
70 The test independently shifted the Q
register and a gp register to the left
using SFTBL0. The shift failed. DL,CT
71 The test independently shifted the Q
register and a gp register to the
right using SFTBR0. The shift failed. DL,CT
72 Zero-extend word mode, transferring
data from memory to memory failed. DL,CT,MEM
73 Zero-extend byte mode, tranferring
data from memory to memory failed. DL,CT,MEM
74 Sign-extended (with 1s) word mode failed.
This tests the 1s-word. DL,CT,MEM
75 Sign-extended (with 0s) word mode failed.
This tests the 1s-word. DL,CT,MEM
7A Unique address error. The test
wrote an address to the CA
register. It then compared the
original address with the address
in the register, and the addresses
were different. AG,AT
7B Unique address error. The test
stored the same address in both
the CA register and another
location. The address in the CA
should have pointed to the second
location. The value in the CA,
however, was incorrect and
differed from the value in the
second location. MEM,AT
7C Complement unique address data error MEM,AT
7D Memory data compare error. The
routine wrote some data to
location 0x4. It then read 0x4
and found that the data was
inaccurate. MEM,AT
7E Memory data compare error; expected
all zeroes MEM,AT
7F Memory data compare error; expected
all ones MEM,AT
80 Incorrect cache address; CA was not
equal to 1 AG,CT,AT
81 Incorrect cache address; CA was not
equal to 2 AG,AT
82 Incorrect cache address; CA was not
equal to 3 AG,AT
83 Incorrect cache address; CA was not
equal to 4 AG,AT
84 Incorrect cache address; CA was not
equal to 5 AG,AT
85 Incorrect cache address; CA was not
equal to 6 AG,AT
86 Incorrect cache address; CA was not
equal to 7 AG,AT
87 Incorrect cache address; CA was not
equal to 8 AG,AT
88 Incorrect cache address; CA was not
equal to 9 AG,AT
89 Incorrect cache address; CA was not
equal to a AG,AT
8a Incorrect cache address; CA was not
equal to b AG,AT
8b Incorrect cache address; CA was not
equal to c AG,AT
8c Incorrect cache address; CA was not
equal to d AG,AT
8d Incorrect cache address; CA was not
equal to e AG,AT
8e Incorrect cache address; CA was not
equal to f AG,AT
8f Incorrect cache address; CA was not
equal to 10 AG,AT
90 AC was changed following sameac.
The test used a particular address
with an instruction and wrote that
address to the address control
(AC) area. It also stored the
address in a temporary location.
After executing sameac, the
routine expected to find the same
address in the AC that it found in
the temporary location. The two
addresses, however, were not the
same. CT,AG
91 AC was changed following sameacp.
This error is similar to error
number 0x90. The routine used the
same method to check the sameacp
function. (In addition to the
operations performed by sameac,
the sameacp function preserves the
addressing mode of the instruction
and turns on a bit that indicates
use of a physical address.) AT,AG
92 AC was changed following sameac.
See the description of error 0x90. CT,AG
93 AC was changed following sameacp.
See the description of error 0x91. CT,AG
94 Original CA was destroyed after a
translation buffer operation (Tbop). AG,CT
95 Incorrect data was in the stack
pointer following a data-loop-to-
SP (dl2sp) function. AG,CT
96 After executing the last-stack-
pointer-to-CA-register (lsp2ca)
function, the test found incorrect
data in the location that stored
the last stack pointer. AG,CT
97 Incorrect data was in the system base
register (SBR). AG,CT
98 Incorrect data was in the P0 space
base register (P0BR). AG,CT
99 Incorrect data was in the P1 space
base register (P1BR). AG,CT
9a Incorrect data was in the P2 space
base register (P2BR). AG,CT
9b Incorrect data was in the system length
register (SLR). AG,CT
9c Incorrect data was in the P0 space
length register (P0LR). AG,CT
9d Incorrect data was in the P1 space
length register (P1LR). AG,CT
9e After decrementing the address stored
in r0, the test found that the
resulting address was incorrect. AG,CT
9f After decrementing the address stored
in r2, the test found that the
resulting address was incorrect. AG,CT
a0 After decrementing the address stored
in r4, the test found that the
resulting address was incorrect. AG,CT
a1 After decrementing the address stored
in r8, the test found that the
resulting address was incorrect. AG,CT
a2 After decrementing the address stored
in r15, the test found that the
resulting address was incorrect. AG,CT
a3 After adding the contents of r0 to
a displacement (displ), the test
found that the resulting offset
was incorrect. AG,CT
a4 After adding the contents of r2 to
a displacement (displ), the test
found that the resulting offset
was incorrect. AG,CT
a5 After adding the contents of r4 to
a displacement (displ), the test
found that the resulting offset
was incorrect. AG,CT
a6 After adding the contents of r8 to
a displacement (displ), the test
found that the resulting offset
was incorrect. AG,CT
a7 After adding the contents of r15 to
a displacement (displ), the test
found that the resulting offset
was incorrect. AG,CT
a8 The test generated an address based
on the value in the LIT register
(absrel). The resulting address,
however, was incorrect. AG,CT
a9 After decrementing the contents of
the CA register (decra), the
routine read and detected an
incorrect address. AG,CT
aa After incrementing the contents of
the CA register (incra), the
routine read and detected an
incorrect address. AG,CT
ab Error when controlling L bus (alit) AG,CT
ac The alit function changed the value in
the CA register. AG,CT
ad Incorrect results after a pop AG,CT
ae Incorrect results after a push AG,CT
af After adding the contents of the
stack pointer to an offset, the
test obtained an incorrect value. AG,CT
b0 Incorrect results after subtest E
(lpushl) AG,CT
b1 Incorrect results after subtest F
(pusha) AG,CT
b2 Incorrect data from P2LR AG,CT
b3 Incorrect CA following a push AG,AT
b4 Incorrect SP following a push AG,AT
b5 Incorrect SP following a pop AG,AT
b6 Incorrect CA; 0+0 != 0 AG,AT
b7 Incorrect CA; -1 + (-1) != -2 AG,AT
b8 Incorrect CA; -1 + 1 != 0 AG,AT
b9 Incorrect CA; 1 + (-1) != 0 AG,AT
ba Incorrect CA; As + 5s != -1 AG,AT
bb Incorrect CA; 5s + As != -1 AG,AT
bc Incorrect cache address; CA != ~1 AG,AT
bd Incorrect cache address; CA != ~2 AG,AT
be Incorrect cache address; CA != ~3 AG,AT
bf Incorrect cache address; CA != ~4 AG,AT
c0 A miss did not occur in data cache AT,AG
r3 Contents of cell after purge
r4 Address
r8 Data cache key
r13 Subtest number = 1
c1 A hit did not occur in data cache AT,AG
r10 Address
r13 Subtest number = 2
c2 A miss did not occur in data cache AT,AG
r4 Data bit used by scanner
r5 Data bit used for testing
r7 Scan address
r10 Address
r11 Index of element
r13 Subtest number = 2
c3 A hit did not occur in data cache AT,AG
r8 Current data cache key
r10 Address
r13 Subtest number = 2
c4 A hit did not occur in data cache AT,AG
r10 Address
r13 Subtest number = 2
c5 A hit did not occur in data cache AT,AG
r10 Address
r13 Subtest number = 2
c6 Incorrect cache data word following a
write hit DL,AT
r2 Address
r5 Actual data
r10 Expected data
r13 Subtest number = 3
c7 Incorrect cache data word following a
unique write hit DL,AT
r2 Address
r5 Actual data
r10 Expected data
r13 Subtest number = 3
c8 A miss did not occur in the translation
buffer AT,AG
r2 Address
r13 Subtest number = 4
c9 A miss did not occur in the translation
buffer AT,AG
r2 Address
r13 Subtest number = 4
ca A miss did not occur in the translation
buffer AT,AG
r2 Address
r13 Subtest number = 4
cb A miss did not occur in the translation
buffer AT,AG
r2 Address
r13 Subtest number = 4
cc A hit did not occur in the translation
buffer AT,AG
r2 Address
r13 Subtest number = 5
cd A hit did not occur in the translation
buffer AT,AG
r2 Address
r13 Subtest number = 5
ce A hit did not occur in the translation
buffer AT,AG
r2 Address
r3 Tested data bit
r13 Subtest number = 5
Q Tested space (P0, P1, P2, or system)
cf A hit did not occur in the translation
buffer AT,AG
r2 Address
r9 Translation buffer key
r13 Subtest number = 5
d0 Compare error for write hit of page
table entry AT,MEM
r2 Address
r7 Actual data
r10 Expected data
r13 Subtest number = 6
d1 Incorrect cache address; CA != ~5 AG,AT
d2 Incorrect cache address; CA != ~6 AG,AT
d3 Incorrect cache address; CA != ~7 AG,AT
d4 Incorrect cache address; CA != ~8 AG,AT
d5 Incorrect cache address; CA != ~9 AG,AT
d6 Incorrect cache address; CA != ~A AG,AT
d7 Incorrect cache address; CA != ~B AG,AT
d8 Incorrect cache address; CA != ~C AG,AT
d9 Incorrect cache address; CA != ~D AG,AT
da Incorrect cache address; CA != ~E AG,AT
db Incorrect cache address; CA != ~F AG,AT
dc Incorrect cache address; CA != ~10 AG,AT
df Incorrect operand address; 0def0000
plus ffff IP,DL
e0 Data compare error in IP registers;
expected all ones IP,CT
e1 Data compare error in IP registers;
walking ones test IP,CT
e2 Data compare error in IP registers;
walking zeroes test IP,CT
e3 Instruction address counter error IP,CT
e4 Instruction fetch error LIA incorrect IP,CT
e5 Incorrect PC after instruction fetch IP,CT
e6 Unable to set macro Z flag DL,CT
e7 Unable to set macro N flag DL,CT
e8 Unable to set macro C flag DL,CT
e9 Unable to set macro V flag DL,CT
ea Incorrect PC following a branch.
With Z set, the test should have
branched to a particular location. IP,CT
eb Incorrect PC following a branch.
With Z clear, the test should have
branched to a particular location. IP,CT
ec Incorrect PC following a branch.
With N set, the test should have
branched to a particular location. IP,CT
ed Incorrect PC following a branch.
With N clear, the test should have
branched to a particular location. IP,CT
ee Wrong literal (zero-extend byte) IP,DL
ef Wrong PC (zero-extend byte) IP,DL
f0 Wrong literal (sign-extend byte) IP,DL
f1 Wrong PC (sign-extend byte) IP,DL
f2 Wrong literal (zero-extend word) IP,DL
f3 Wrong PC (zero-extend word) IP,DL
f4 Wrong literal (sign-extend word) IP,DL
f5 Wrong PC (sign-extend word) IP,DL
f6 Wrong literal (zero-extend longword) IP,DL
f7 Wrong PC (zero-extend longword) IP,DL
f8 Wrong literal (sign-extend longword) IP,DL
f9 Wrong PC (sign-extend longword) IP,DL
fa Wrong literal of aaaaaaaa IP,DL
fb Wrong PC (move lit of aaaaaaaa) IP,DL
fc Wrong literal of 33333333 IP,DL
fd Wrong PC (move lit of 33333333) IP,DL
fe Incorrect operand address; 0def0000
plus 0000 IP,DL
#poc2
01 Failed decode of halt instruction IP,CT
02 Failed decode of nop instruction IP,CT
03 Failed decode of rei instruction IP,CT
04 Failed decode of movblk instruction IP,CT
05 Failed decode of movl instruction;
movl r0 to r5 IP,CT
06 Failed decode of movl instruction;
movl r5 to r0 IP,CT
07 Failed decode of movl instruction;
movl ra to r5 IP,CT
08 Failed decode of movl instruction;
movl r5 to ra IP,CT
09 Failed decode of movl instruction;
movl byte literal to r5 IP,CT
0a Failed decode of movl instruction;
movl byte literal to ra IP,CT
0b Failed decode of movl instruction;
movl word literal to r5 IP,CT
0c Failed decode of movl instruction;
movl word literal to ra IP,CT
0d Failed decode of movl instruction;
movl longword literal to r5 IP,CT
0e Failed decode of movl instruction;
movl longword literal to ra IP,CT
0f Failed decode of ret instruction IP,CT
10 Failed decode of clrb instruction IP,CT
11 Failed decode of clrw instruction IP,CT
12 Failed decode of clrl instruction IP,CT
13 Failed decode of push instruction IP,CT
14 Failed decode of add3 instruction IP,CT
15 Failed decode of call instruction;
stack pointer incorrect CT,IP
16 Failed decode of call instruction;
r0 not saved properly CT,IP
17 Failed decode of call instruction;
r1 not saved properly CT,IP
18 Failed decode of call instruction;
r2 not saved properly CT,IP
19 Failed decode of call instruction;
r3 not saved properly CT,IP
1a Failed decode of call instruction;
r4 not saved properly CT,IP
1b Failed decode of call instruction;
r5 not saved properly CT,IP
1c Failed decode of call instruction;
r6 not saved properly CT,IP
1d Failed decode of call instruction;
r7 not saved properly CT,IP
1e Failed decode of call instruction;
r8 not saved properly CT,IP
1f Failed decode of call instruction;
r9 not saved properly CT,IP
20 Failed decode of call instruction;
ra not saved properly CT,IP
21 Failed decode of call instruction;
rb not saved properly CT,IP
22 Failed decode of call instruction;
rc not saved properly CT,IP
23 Failed decode of call instruction;
return address not saved properly CT,IP
24 Failed decode of call instruction;
mask + reg save not saved properly CT,IP
25 Failed decode of call instruction;
reg d not saved properly CT,IP
26 Failed decode of movl instruction;
movl r5 to cache (auto decr SP) IP,CT
27 Failed decode of movl instruction;
movl cache (auto incr SP) to r5 IP,CT
28 Failed decode of movl instruction;
movl cache (auto incr deferred) to SP IP,CT
29 Failed decode of movl instruction;
movl cache (r5 deferred) to r4 IP,CT
2a Failed decode of movl instruction;
movb cache (r5 + byte) to r4 IP,CT
2b Failed decode of movl instruction;
movw cache (r5 + word) to r4 IP,CT
2c Failed decode of movl instruction;
movl cache (r5 + longword) to r4 IP,CT
2d Failed decode of movl instruction;
movl index by r5 to r4 AG,IP
2e Failed decode of movl instruction;
movw index by r5 to r4 AG,IP
2f Failed decode of movl instruction;
movb index by r5 to r4 AG,IP
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