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1.1 root 1: /*
2: ------------------------------------------
3: Must include <h/types.h> and <h/buf.h>
4: ------------------------------------------
5: */
6:
7: #define DRINTV 0x9c /* Has to match with ml/scb.s */
8: #define DRADDMOD 0x01 /* Addr modifier used to access TAHOE memory */
9: #define DR_ZERO 0
10: #define DRPRI (PZERO+1)
11:
12: #define DR_TICK 600 /* Default # of clock ticks between call
13: to local timer watchdog routine */
14: #define DR_TOCK 2 /* default # of calls to local watch dog
15: before an IO or wait is determined to
16: have timeout */
17:
18:
19: struct rsdevice {
20: ushort dr_cstat; /* Control & status registers */
21: ushort dr_data; /* Input/Ouptut data registers */
22: char dr_addmod; /* Address modifier for DMA */
23: char dr_intvect; /* Interrupt vector */
24: ushort dr_pulse; /* Pulse command register */
25: ushort dr_xx08; /* Not used */
26: ushort dr_xx0A; /* Not used */
27: ushort dr_xx0C; /* Not used */
28: ushort dr_xx0E; /* Not used */
29: ushort dr_xx10; /* Not used */
30: ushort dr_walo; /* Low DMA address register --when written-- */
31: ushort dr_range; /* DMA range counter */
32: ushort dr_ralo; /* Low DMA address register --when read-- */
33: ushort dr_xx18; /* Not used */
34: ushort dr_wahi; /* High DMA address register --when written-- */
35: ushort dr_xx1C; /* Not used */
36: ushort dr_rahi; /* High DMA address register --when read-- */
37: };
38:
39:
40: struct dr_aux {
41: struct rsdevice *dr_addr; /* Physical addr of currently active DR11 */
42: struct buf *dr_actf; /* Pointers to DR11's active buffers list */
43: unsigned int dr_flags; /* State: Hold open, active,... */
44: ushort dr_cmd; /* Hold cmd placed here by ioctl
45: for later execution by rsstrategy() */
46: ushort dr_op; /* Current operation: DR_READ/DR_WRITE */
47: long dr_bycnt; /* Total byte cnt of current operation */
48: /* decremented by completion interrupt */
49: caddr_t dr_oba; /* original xfer addr, count */
50: long dr_obc;
51: unsigned long
52: rtimoticks, /* No of ticks before timing out on no stall
53: read */
54: wtimoticks, /* No of ticks before timing out on no stall
55: write */
56: currenttimo; /* the number of current timeout call to
57: omrwtimo() */
58: ushort dr_istat; /* Latest interrupt status */
59: struct buf dr_buf;
60:
61: /*ushort dr_time; /* # of ticks until timeout */
62: /*ushort dr_tock; /* # of ticks accumulated */
63: /*ushort dr_cseq; /* Current sequence number */
64: /*ushort dr_lseq; /* Last sequence number */
65: };
66:
67: /* Command used by drioctl()
68: */
69: struct dr11io {
70: ushort arg[8];
71: };
72:
73: #define RSADDR(unit) ((struct rsdevice *)drinfo[unit]->ui_addr)
74:
75: /* Control register bits */
76: #define RDMA 0x8000 /* reset DMA end-of-range flag */
77: #define RATN 0x4000 /* reset attention flag */
78: #define RPER 0x2000 /* reset device parity error flag */
79: #define MCLR 0x1000 /* master clear board and INT device */
80: #define CYCL 0x0100 /* forces DMA cycle if DMA enabled */
81: #define IENB 0x0040 /* enables interrupt */
82: #define FCN3 0x0008 /* func. bit 3 to device (FNCT3 H) */
83: #define FCN2 0x0004 /* func. bit 2 to device (FNCT2 H) */
84: /* also asserts ACLO FCNT2 H to device */
85: #define FCN1 0x0002 /* func. bit 1 to device (FNCT1 H) */
86: #define GO 0x0001 /* enable DMA and pulse GO to device */
87:
88: /* Status register bits */
89: #define DMAF 0x8000 /* indicates DMA end-of-range */
90: #define ATTF 0x4000 /* indicates attention false-to-true */
91: #define ATTN 0x2000 /* current state of ATTENTION H input */
92: #define PERR 0x1000 /* Set by external parity error */
93: #define STTA 0x0800 /* STATUS A H input state */
94: #define STTB 0x0400 /* STATUS B H input state */
95: #define STTC 0x0200 /* STATUS C H input state */
96: #define REDY 0x0080 /* board ready for cmd (dma not on) */
97: #define IENF 0x0040 /* Interrupt enabled if on */
98: #define BERR 0x0020 /* Set if bus error during DMA */
99: #define TERR 0x0010 /* Set if bus timeout during DMA */
100: #define FC3S 0x0008 /* State of FCN3 latch */
101: #define FC2S 0x0004 /* State of FCN2 latch */
102: #define FC1S 0x0002 /* State of FCN1 latch */
103: #define DLFG 0x0001 /* 0 -> IKON-10083 *** 1 -> IKON-10077 */
104:
105: /* Pulse command register bits */
106: #define SMSK 0x0040 /* pulse interrupt mask on: Set IENB */
107: #define RMSK 0x0020 /* pulse interrupt mask off: Reset IENB */
108:
109:
110: /*
111: * DR11 driver's internal flags -- to be stored in dr_flags
112: */
113: #define DR_FMSK 0x0000E /* function bits mask */
114: #define DR_OPEN 0x00001 /* This dr11 has been opened */
115: #define DR_PRES 0x00002 /* This dr11 is present */
116: #define DR_ACTV 0x00004 /* waiting for end-of-range */
117: #define DR_ATWT 0x00008 /* waiting for attention interrupt */
118: #define DR_ATRX 0x00010 /* attn received-resets when read */
119: #define DR_TMDM 0x00020 /* timeout waiting for end-of-range */
120: #define DR_TMAT 0x00040 /* timeout waiting for attention */
121: #define DR_DMAX 0x00080 /* end-of-range interrupt received */
122: #define DR_PCYL 0x00100 /* set cycle with next go */
123: #define DR_DFCN 0x00200 /* donot update function bits until next go */
124: #define DR_DACL 0x00400 /* defer alco pulse until go */
125: #define DR_LOOPTST 0x02000 /* This dr11 is in loopback test mode */
126: #define DR_LNKMODE 0x04000 /* This dr11 is in link mode */
127: #define DR_NORSTALL 0x10000 /* Device is set to no stall mode for reads. */
128: #define DR_NOWSTALL 0x20000 /* Device is set to no stall mode for writes. */
129: #define DR_TIMEDOUT 0x40000 /* The device timed out on a stall mode R/W */
130:
131: /*
132: * DR11 driver's internal flags -- to be stored in dr_op
133: */
134: #define DR_READ FCN1
135: #define DR_WRITE 0
136:
137: /*
138: * Ioctl commands
139: */
140: #define DRWAIT _IOWR(d,1,long)
141: #define DRPIOW _IOWR(d,2,long)
142: #define DRPACL _IOWR(d,3,long)
143: #define DRDACL _IOWR(d,4,long)
144: #define DRPCYL _IOWR(d,5,long)
145: #define DRDFCN _IOWR(d,6,long)
146: #define DRRPER _IOWR(d,7,long)
147: #define DRRATN _IOWR(d,8,long)
148: #define DRRDMA _IOWR(d,9,long)
149: #define DRSFCN _IOWR(d,10,long)
150:
151: #define DRSETRSTALL _IOWR(d,13,long)
152: #define DRSETNORSTALL _IOWR(d,14,long)
153: #define DRGETRSTALL _IOWR(d,15,long)
154: #define DRSETRTIMEOUT _IOWR(d,16,long)
155: #define DRGETRTIMEOUT _IOWR(d,17,long)
156: #define DRSETWSTALL _IOWR(d,18,long)
157: #define DRSETNOWSTALL _IOWR(d,19,long)
158: #define DRGETWSTALL _IOWR(d,20,long)
159: #define DRSETWTIMEOUT _IOWR(d,21,long)
160: #define DRGETWTIMEOUT _IOWR(d,22,long)
161: #define DRWRITEREADY _IOWR(d,23,long)
162: #define DRREADREADY _IOWR(d,24,long)
163: #define DRBUSY _IOWR(d,25,long)
164: #define DRRESET _IOWR(d,26,long)
165:
166: /* The block size for buffering and DMA transfers. */
167: /* OM_BLOCKSIZE must be even and <= 32768. Multiples of 512 are prefered. */
168: #define OM_BLOCKSIZE 32768
169:
170:
171: /* --- Define ioctl call used by dr11 utility device -- */
172:
173: #define DR11STAT _IOWR(d,1,struct dr11io) /* Get status dr11, unit
174: number is dr11io.arg[0] */
175: #define DR11LOOP _IOR(d,2,struct dr11io) /* Perform loopback test */
176:
177: /* ---------------------------------------------------- */
178:
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