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1.1 root 1: #include "dr.h"
2: #if NDR > 0
3:
4: /* DRV11-W DMA interface driver utility
5: *
6: */
7:
8: #include "../machine/pte.h"
9: #include "../machine/mtpr.h"
10: #include "../h/param.h"
11: #include "../h/conf.h"
12: #include "../h/dir.h"
13: #include "../h/user.h"
14: #include "../h/proc.h"
15: #include "../h/map.h"
16: #include "../h/ioctl.h"
17: #include "../h/buf.h"
18: #include "../h/vm.h"
19: #include "../h/uio.h"
20:
21: #include "../vba/vbavar.h"
22: #include "../h/drreg.h"
23:
24: extern struct vba_device *drinfo[];
25: extern struct dr_aux dr_aux[];
26:
27: #define YES 1
28: #define NO 0
29:
30: #define RSUNIT(dev) (minor(dev) & 7)
31:
32: #define SPL_UP spl8
33:
34: /* -------- Per-unit data -------- */
35:
36: extern struct dr_aux dr_aux[];
37: extern struct vba_device *drinfo[];
38:
39: dr11open (dev, flag)
40: dev_t dev;
41: int flag;
42: {
43: if (!(suser())) return(EPERM);
44: return 0;
45: }
46:
47: dr11close (dev)
48: dev_t dev;
49: {
50: return;
51: }
52:
53:
54: dr11ioctl(dev, cmd, data, flag)
55: dev_t dev;
56: int cmd;
57: struct dr11io *data;
58: int flag;
59: {
60: register int unit = data->arg[0];
61: register struct dr_aux *dra;
62: register struct rsdevice *rsaddr;
63: struct dr11io dio;
64: ushort temp, s, errcode, status;
65:
66: dra = &dr_aux[unit];
67: if (!(dra->dr_flags & DR_PRES)) return(ENODEV);
68: rsaddr = RSADDR(unit);
69: switch (cmd) {
70:
71: case DR11STAT:
72: /* Copy back dr11 status to user */
73: data->arg[0] = dra->dr_flags;
74: data->arg[1] = rsaddr->dr_cstat;
75: data->arg[2] = dra->dr_istat; /* Status reg. at last interrupt */
76: data->arg[3] = rsaddr->dr_data; /* P-i/o input data */
77: status = (ushort)((rsaddr->dr_addmod << 8) & 0xff00);
78: data->arg[4] = status | (ushort)(rsaddr->dr_intvect & 0xff);
79: data->arg[5] = rsaddr->dr_range;
80: data->arg[6] = rsaddr->dr_rahi;
81: data->arg[7] = rsaddr->dr_ralo;
82: break;
83: case DR11LOOP:
84: /* Perform loopback test -- MUST HAVE LOOPBACK CABLE ATTACHED --
85: Test results are printed on system console */
86: dr11loop(rsaddr,dra,unit);
87: break;
88:
89: default:
90: break;
91: }
92:
93: #ifdef DR_DEBUG
94: /*
95: +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
96: printf("\n\t------------- DR11 Status ------------");
97: printf("\n\t dr_flags CSR istat idata modvec dmacnt hiadr loadr");
98: printf("\n\t %lx %lx %lx %lx %lx %ld %lx %lx\n",
99: data->arg[0],data->arg[1],data->arg[2],data->arg[3] & 0xffff,
100: data->arg[4],data->arg[5],data->arg[6],data->arg[7]);
101: +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
102: */
103: #endif
104:
105: return 0;
106: }
107:
108: #define NPAT 2
109: #define DMATBL 20
110: ushort tstpat[DMATBL] = { 0xAAAA, 0x5555};
111: long DMAin = 0;
112:
113: dr11loop(dr,dra,unit)
114: struct rsdevice *dr;
115: struct dr_aux *dra;
116: long unit;
117: { register long result, ix;
118: long baddr, wait;
119:
120: dr->dr_cstat = MCLR; /* Clear board & device, disable intr */
121:
122: /* Perform loopback test -- MUST HAVE LOOPBACK CABLE ATTACHED --
123: Test results are printed on system console */
124: printf("\n\t ----- DR11 unit %ld loopback test -----",unit);
125:
126: printf("\n\t Program I/O ...");
127: for (ix=0;ix<NPAT;ix++) {
128: dr->dr_data = tstpat[ix]; /* Write to Data out register */
129: result = (dr->dr_data & 0xFFFF); /* Read it back */
130: if (result != tstpat[ix]) {
131: printf("Failed, expected : %lx --- actual : %lx",
132: tstpat[ix],result);
133: return;
134: }
135: }
136:
137: printf("OK\n\t Functions & Status Bits ...");
138: dr->dr_cstat = (FCN1 | FCN3);
139: result = dr->dr_cstat & 0xffff; /* Read them back */
140: if ((result & (STTC | STTA)) != (STTC |STTA)) {
141: printf("Failed, expected : %lx --- actual : %lx, ISR:%lx",
142: (STTA|STTC),(result & (STTA|STTC)), result);
143: return;
144: }
145: dr->dr_cstat = FCN2;
146: result = dr->dr_cstat & 0xffff; /* Read them back */
147: if ((result & STTB) != STTB) {
148: printf("Failed, expected : %lx --- actual : %lx, ISR:%lx",
149: STTB,(result & STTB), result);
150: return;
151: }
152:
153: printf("OK\n\t DMA output ...");
154:
155: if (DMAin) goto dmain;
156:
157: /* Initialize DMA data buffer */
158: for(ix=0;ix<DMATBL;ix++) tstpat[ix] = 0xCCCC + ix;
159: tstpat[DMATBL-1] = 0xCCCC; /* Last word output */
160:
161: /* Setup normal DMA */
162: baddr = (long)vtoph(0,tstpat); /* Virtual --> physical */
163: dr->dr_walo = (ushort)((baddr >> 1) & 0xffff);
164: dr->dr_wahi = (ushort)((baddr >> 17) & 0x7fff);
165:
166: /* Set DMA range count: (number of words - 1) */
167: dr->dr_range = (ushort)(DMATBL - 1);
168:
169: /* Set address modifier code to be used for DMA access to memory */
170: dr->dr_addmod = (char)DRADDMOD;
171:
172: /* Clear dmaf and attf to assure a clean dma start, also disable
173: attention interrupt
174: */
175: dr->dr_pulse = (ushort)(RDMA|RATN|RMSK); /* Use pulse register */
176: dr->dr_cstat = (GO|CYCL); /* GO...... */
177:
178: /* Wait for DMA complete; REDY and DMAF are true in ISR */
179: wait = 0;
180: while ((result=(dr->dr_cstat & (REDY | DMAF))) != (REDY|DMAF)) {
181: printf("\n\tWait for DMA complete...ISR : %lx",result);
182: if (++wait > 5) {
183: printf("\n\t DMA output fails...timeout!!, ISR:%lx",
184: result);
185: return;
186: }
187: }
188:
189: result = dr->dr_data & 0xffff; /* Read last word output */
190: if (result != 0xCCCC) {
191: printf("\n\t Fails, expected : %lx --- actual : %lx",
192: 0xCCCC,result);
193: return;
194: }
195:
196: printf("OK\n\t DMA input ...");
197:
198: dmain:
199: dr->dr_data = 0x1111; /* DMA input data */
200: /* Setup normal DMA */
201: baddr = (long)vtoph(0,tstpat); /* Virtual --> physical */
202: dr->dr_walo = (ushort)((baddr >> 1) & 0xffff);
203: dr->dr_wahi = (ushort)((baddr >> 17) & 0x7fff);
204:
205: /* Set DMA range count: (number of words - 1) */
206: dr->dr_range = (ushort)(DMATBL - 1);
207:
208: /* Set address modifier code to be used for DMA access to memory */
209: dr->dr_addmod = (char)DRADDMOD;
210: /* Set FCN1 in ICR to DMA in*/
211: dr->dr_cstat = FCN1;
212:
213: if (!(dra->dr_flags & DR_LOOPTST)) {
214: /* Use pulse reg */
215: dr->dr_pulse = (ushort)(RDMA|RATN|RMSK|CYCL|GO);
216: /* Wait for DMA complete; REDY and DMAF are true in ISR */
217: wait = 0;
218: while ((result=(dr->dr_cstat & (REDY | DMAF)))
219: != (REDY|DMAF)) {
220: printf("\n\tWait for DMA to complete...ISR:%lx",result);
221: if (++wait > 5) {
222: printf("\n\t DMA input timeout!!, ISR:%lx",
223: result);
224: return;
225: }
226: }
227: }
228: else {
229: /* Enable DMA e-o-r interrupt */
230: dr->dr_pulse = (ushort)(IENB|RDMA|RATN|CYCL|GO);
231: /* Wait for DMA complete; DR_LOOPTST is false in dra->dr_flags*/
232: wait = 0;
233: while (dra->dr_flags & DR_LOOPTST) {
234: result = dr->dr_cstat & 0xffff;
235: printf("\n\tWait for DMA e-o-r intr...ISR:%lx",result);
236: if (++wait > 7) {
237: printf("\n\t DMA e-o-r timeout!!, ISR:%lx",
238: result);
239: dra->dr_flags &= ~DR_LOOPTST;
240: return;
241: }
242: }
243: dra->dr_flags |= DR_LOOPTST;
244: }
245:
246: mtpr(tstpat,P1DC); /* Purge cache */
247: mtpr((0x3ff+(long)tstpat),P1DC);
248: for(ix=0;ix<DMATBL;ix++) {
249: if (tstpat[ix] != 0x1111) {
250: printf("\n\t Fails, ix:%ld,expected : %lx --- actual : %lx",
251: ix,0x1111,tstpat[ix]);
252: return;
253: }
254: }
255: if (!(dra->dr_flags & DR_LOOPTST)) {
256: dra->dr_flags |= DR_LOOPTST;
257: printf(" OK..\n\tDMA end of range interrupt...");
258: goto dmain;
259: }
260:
261:
262: printf(" OK..\n\tAttention interrupt....");
263: /* Pulse FCN2 in pulse register with IENB */
264: dr->dr_pulse = (ushort)(IENB|RDMA);
265: dr->dr_pulse = (ushort)FCN2;
266:
267: /* Wait for ATTN interrupt; DR_LOOPTST is false in dra->dr_flags*/
268: wait = 0;
269: while (dra->dr_flags & DR_LOOPTST) {
270: result = dr->dr_cstat & 0xffff;
271: printf("\n\tWait for Attention intr...ISR:%lx",result);
272: if (++wait > 7) {
273: printf("\n\t Attention interrupt timeout!!, ISR:%lx",
274: result);
275: dra->dr_flags &= ~DR_LOOPTST;
276: return;
277: }
278: }
279: dra->dr_flags &= ~DR_LOOPTST;
280: printf(" OK..\n\tDone...");
281: }
282:
283: #endif
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