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1.1 root 1: /*
2: ** Header file for the VDDC (Versabus Direct Disk Controller) Driver
3: */
4:
5: /*
6: ** DCB Command Codes
7: */
8:
9: #define RD 0x80 /* Read Data */
10: #define FTR 0xc0 /* Full Track Read */
11: #define RAS 0x90 /* Read and Scatter */
12: #define C 0xa0 /* Compare */
13: #define FTC 0xe0 /* Full Track Compare */
14: #define RHDE 0x180 /* Read Header, Data & ECC (not used) */
15: #define WD 0x00 /* Write Data */
16: #define FTW 0x40 /* Full Track Write */
17: #define WTC 0x20 /* Write Then Compare */
18: #define FTWTC 0x60 /* Full Track Write Then Compare */
19: #define GAW 0x10 /* Gather and Write */
20: #define WDE 0x100 /* Write Data & ECC (not used) */
21: #define FSECT 0x900 /* Format Sector */
22: #define GWC 0x30 /* Gather Write & Compare */
23: #define VDSTART 0x800 /* Start drives */
24: #define VDRELEASE 0xa00 /* Stop drives */
25: #define SEEK 0xb00 /* Seek */
26: #define INIT 0xc00 /* Initialize VDDC */
27: #define DIAG 0xd00 /* Diagnose (self-test) VDDC */
28: #define RSTCFG 0xe00 /* Reset/Configure VDDC/DDI/Drive(s) */
29: #define VDSTATUS 0xf00 /* VDDC Status */
30:
31: #define ABORT 0x80000000 /* ABORT active i/o */
32:
33: /*
34: ** Error / Status Symbolic Constants
35: */
36:
37: #define HCRCERR 0x1 /* Header CRC Error */
38: #define HCMPERR 0x2 /* Header Compare Error */
39: #define WPTERR 0x4 /* Write Protect Error/Status */
40: #define CTLRERR 0x8 /* Controller Error */
41: #define DSEEKERR 0x10 /* Disk Seek Error */
42: #define UCDATERR 0x20 /* Uncorrectable Data Error */
43: #define NOTCYLERR 0x40 /* Not on Cylinder Error */
44: #define DRVNRDY 0x80 /* Drive Not Ready Error/Status */
45: #define ALTACC 0x100 /* Alternate (track) accessed Status */
46: #define SEEKSTRT 0x200 /* Seek Started Status */
47: #define INVDADR 0x400 /* Invalid Disk Address Error */
48: #define DNEMEM 0x800 /* Non-Existant Memory Error */
49: #define PARERR 0x1000 /* Memory Parity Error */
50: #define DCOMPERR 0x2000 /* Data Compare Error */
51: #define DDIRDY 0x4000 /* DDI Ready Error/Status */
52: #define OPABRT 0x8000 /* Operator Abort (Host) Error/Status */
53: #define DSERLY 0x10000 /* Data Strobe Early */
54: #define DSLATE 0x20000 /* Data Strobe Late */
55: #define TOPLUS 0x40000 /* Track Offset Plus */
56: #define TOMNUS 0x80000 /* Track Offset Minus */
57: #define CPDCRT 0x100000 /* Cntlr Performed Data Correction */
58: #define HRDERR 0x200000 /* Hard Error */
59: #define SFTERR 0x400000 /* Soft Error (retry succesful) */
60: #define ANYERR 0x800000 /* Any Error */
61: #define INVCMD 0x1000000 /* Programmer error */
62:
63:
64: /*
65: ** DCB Status Symbolic Constants
66: */
67:
68: #define DCBABT 0x10000000 /* DCB Aborted */
69: #define DCBUSC 0x20000000 /* DCB Unsuccesfully Completed */
70: #define DCBCMP 0x40000000 /* DCB Complete */
71: #define DCBSTR 0x80000000 /* DCB Started */
72:
73: /*
74: ** MDCB Status Symbolic Constants
75: */
76:
77: #define CTLRBSY 0x10000000 /* Cntlr Busy */
78: #define INTCCDE 0x60000000 /* Interrupt Cause Code */
79: #define DCBINT 0x80000000 /* DCB Interrupt Flag */
80:
81:
82: /*
83: ** Hard Error Types
84: */
85:
86: #define HTYPES (HCRCERR|HCMPERR|WPTERR|CTLRERR|DSEEKERR|UCDATERR|NOTCYLERR| \
87: DRVNRDY|INVDADR|DNEMEM|PARERR|DCOMPERR)
88:
89:
90: /*
91: ** Errors
92: */
93:
94: #define ERRS 0x3FFF
95: #define CANRETRY (CTLRERR|DSEEKERR|NOTCYLERR|DCOMPERR|UCDATERR| \
96: PARERR|DNEMEM|HCRCERR|HCMPERR)
97: /*
98: ** VDDC Interrupt Modes
99: */
100:
101: #define NOINT 0x0 /* No Interrupt */
102: #define INTERR 0x2 /* Interrupt on Error */
103: #define INTSUC 0x1 /* Interrupt on Success */
104: #define INTDONE 0x3 /* Interrupt on Error or Success */
105:
106:
107: /* Control and Status bit assignments */
108: #define CS_SCS 0xf /* Status Change Source (drive number) */
109: #define CS_ELC 0x10 /* Error on Last Command */
110: #define CS_ICC 0x60 /* Interupt Cause Code */
111: #define ICC_NOI 0x00 /* No interupt */
112: #define ICC_DUN 0x20 /* No interupt */
113: #define ICC_ERR 0x40 /* No interupt */
114: #define ICC_SUC 0x60 /* No interupt */
115: #define CS_GO 0x80 /* Go bit (controller working) */
116: #define CS_BE 0x100 /* Buss Error */
117: #define CS_BOK 0x4000 /* Board O.K. */
118: #define CS_SFL 0x8000 /* System fail */
119: #define CS_LEC 0xff000000 /* Last Error Code */
120:
121: /* Status word bit assignments */
122: #define STA_UR 0x1 /* Unit Ready */
123: #define STA_OC 0x2 /* On Cylinder */
124: #define STA_SE 0x4 /* Seek Error */
125: #define STA_DF 0x8 /* Drive Fault */
126: #define STA_WP 0x10 /* Write Protected */
127: #define STA_US 0x20 /* Unit Selected */
128:
129: /* Interupt Control Field bit assignments */
130: #define ICF_IPL 0x7 /* Interupt Priority Level */
131: #define ICF_IEN 0x8 /* Interupt ENable */
132: #define ICF_IV 0xff00 /* Interupt Vector */
133:
134: /* Transfer Control Format bit assignments */
135: #define TCF_AM 0xff /* Address Modifier */
136: #define AM_SNPDA 0x01 /* Standard Non-Privileged Data Access */
137: #define AM_SASA 0x81 /* Standard Ascending Sequential Access */
138: #define AM_ENPDA 0xf1 /* Extended Non-Privileged Data Access */
139: #define AM_EASA 0xe1 /* Extended Ascending Sequential Access */
140: #define TCF_BTE 0x800 /* Block Transfer Enable */
141:
142: /* Controller Configuration Flags bit assignments */
143: #define CCF_STS 0x1 /* Sectors per Track Selectable */
144: #define CCF_EAV 0x2 /* Enable Auto Vector */
145: #define CCF_ERR 0x4 /* Enable Reset Register */
146: #define CCF_XMD 0x60 /* XMD transfer mode (buss size) */
147: #define XMD_8BIT 0x20 /* Do only 8 bit transfers */
148: #define XMD_16BIT 0x40 /* Do only 16 bit transfers */
149: #define XMD_32BIT 0x60 /* Do only 32 bit transfers */
150: #define CCF_BSZ 0x300 /* Burst SiZe */
151: #define BSZ_16WRD 0x000 /* 16 word transfer burst */
152: #define BSZ_12WRD 0x100 /* 12 word transfer burst */
153: #define BSZ_8WRD 0x200 /* 8 word transfer burst */
154: #define BSZ_4WRD 0x300 /* 4 word transfer burst */
155: #define CCF_ENP 0x1000 /* ENable Parity */
156: #define CCF_EPE 0x2000 /* Enable Parity Errors */
157: #define CCF_EDE 0x10000 /* Error Detection Enable */
158: #define CCF_ECE 0x20000 /* Error Correction Enable */
159:
160: /* Diagnostic register definitions */
161:
162: #define DIA_DC 0x7f /* Dump count mask */
163: #define DIA_DWR 0x80 /* Dump Write / Read flag */
164: #define DIA_ARE 0x100 /* Auto Rebuild Enable */
165: #define DIA_CEN 0x200 /* Call ENable flag */
166: #define DIA_KEY 0xAA550000 /* Reset KEY */
167:
168: /* Sector Header bit assignments */
169: #define VDMF 0x8000 /* Manufacturer Fault 1=good sector */
170: #define VDUF 0x4000 /* User Fault 1=good sector */
171: #define VDALT 0x2000 /* Alternate Sector 1=alternate */
172: #define VDWPT 0x1000 /* Write Protect 1=Read Only Sector */
173:
174: /* DCB Bit assignments */
175: #define INT_IC 0x3 /* Interupt Control */
176: #define IC_NOI 0x0 /* NO Interupt */
177: #define IC_IOD 0x1 /* Interupt On Done */
178: #define IC_IOE 0x2 /* Interupt On Error */
179: #define IC_IOS 0x3 /* Interupt On Success */
180: #define INT_PBA 0x4 /* Proceed before ACK */
181:
182: /*
183: ** Address of Memory-Mapped I/O Port for VDDC H/W Reset
184: */
185:
186: #define VDDC_RESET(addr, type) { if(type == SMD_ECTLR) { \
187: (addr)->diag_flags=DIA_KEY | DIA_CEN; \
188: (addr)->cdr_mdcb_ptr = \
189: (fmt_mdcb *)0xffffffff; \
190: DELAY(5000000); \
191: } \
192: else { \
193: (addr)->cdr_reset = 0x0; \
194: DELAY(1500000); \
195: } \
196: }
197:
198: /*
199: ** Abort controller operation.
200: */
201:
202: #define VDDC_ABORT(a, type) { if((type) == SMDCTLR) { \
203: movow((ABORT & 0xffff0000)>>16,a) ; \
204: movow(ABORT & 0xffff, (int)(a)+2); \
205: } \
206: else (a)->cdr_mdcb_ptr = (fmt_mdcb *)ABORT; \
207: DELAY(1000000); }
208:
209: /*
210: ** Start i/o to/from controller.
211: */
212:
213: #define VDDC_ATTENTION(ctlr, mdcbadr, type) \
214: { if(type == SMDCTLR) { \
215: movow(((int)mdcbadr & 0xffff0000)>>16,ctlr) ; \
216: movow((int)mdcbadr & 0xffff, (int)(ctlr)+2); \
217: } \
218: else (ctlr)->cdr_mdcb_ptr = mdcbadr; }
219:
220:
221: #define POLLTILLDONE(c, a, x, t) { vdtimeout = 1000*(x); \
222: uncache(&((a)->operrsta)); \
223: while (!(((a)->operrsta) & (DCBCMP | DCBABT))) { \
224: DELAY(1000); \
225: vdtimeout--; \
226: uncache(&((a)->operrsta)); \
227: if (vdtimeout <= 0) { \
228: printf("VDDC: Controller timeout"); \
229: VDDC_ABORT(c, t); \
230: DELAY(30000); \
231: break; \
232: } \
233: } \
234: if((vdtimeout > 0)) \
235: if((t == SMD_ECTLR) && (vdtimeout > 0)) { \
236: uncache(&(c)->cdr_csr); \
237: while((c)->cdr_csr & CS_GO) { \
238: DELAY(50); \
239: uncache(&(c)->cdr_csr); \
240: } \
241: DELAY(500); \
242: } \
243: else DELAY(200); \
244: uncache(&((a)->operrsta)); \
245: }
246:
247:
248: /* Disk Address */
249:
250: typedef struct {
251: char track; /* all 8 bits */
252: char sector; /* all 8 bits */
253: short cylinder; /* low order 12 bits */
254: } dskadr;
255:
256: /* sector formats */
257:
258: typedef union {
259: struct {
260: dskadr hdr_addr;
261: short smd_crc;
262: } smd;
263: struct {
264: dskadr physical;
265: dskadr logical;
266: long smd_e_crc;
267: } smd_e;
268: } fmt_hdr;
269:
270:
271: /* DCB Trailer Formats */
272:
273: /* Read / Write Trailer */
274:
275: typedef struct {
276: char *memadr; /* memory address */
277: unsigned long wcount; /* 16 bit word count */
278: dskadr disk; /* disk address */
279: } trrw;
280:
281: /* Scatter/gather trailer */
282:
283: typedef struct {
284: trrw start_addr;
285: struct {
286: char *nxt_addr;
287: unsigned long nxt_len;
288: } addr_chain[126];
289: } trsg;
290:
291: /* Seek trailer format */
292:
293: typedef struct {
294: dskadr skaddr;
295: } trseek;
296:
297: /* Format Trailer */
298:
299: typedef struct {
300: char *addr; /* data buffer to be filled on sector*/
301: long nsectors; /* # of sectors to be formatted */
302: dskadr disk; /* Disk physical address info */
303: dskadr hdr; /* Header address info */
304: } trfmt;
305:
306:
307: /* Reset / Configure Trailer */
308:
309: typedef struct {
310: long ncyl; /* # cylinders */
311: long nsurfaces; /* # surfaces */
312: long nsectors; /* # sectors */
313: long slip_sec; /* # of slip sectors */
314: } treset;
315:
316:
317: /* DCB Format */
318:
319: typedef struct fmtdcb{
320: struct fmtdcb *nxtdcb; /* next dcb in chain or End of Chain */
321: short intflg; /* interrupt settings and flags */
322: short opcode; /* DCB Command code etc... */
323: long operrsta; /* Error & Status info */
324: short fill; /* not used */
325: char devselect; /* Drive selection */
326: char trailcnt; /* Trailer Word Count */
327: long err_memadr; /* Error memory address */
328: char err_code; /* Error codes for SMD/E */
329: char fill2; /* not used */
330: short err_wcount; /* Error word count */
331: char err_trk; /* Error track/sector */
332: char err_sec; /* Error track/sector */
333: short err_cyl; /* Error cylinder adr */
334: union {
335: trseek sktrail; /* seek command trailer */
336: /* trsg sgtrail; /* Scatter gather trailer */
337: trrw rwtrail; /* read/write trailer */
338: trfmt fmtrail; /* format trailer */
339: treset rstrail; /* reset/configure trailer */
340: } trail;
341: } fmt_dcb;
342:
343:
344: /* MDCB Format */
345:
346: typedef struct {
347: fmt_dcb *firstdcb; /* first dcb in chain */
348: fmt_dcb *procdcb; /* dcb being processed */
349: fmt_dcb *intdcb; /* dcb causing interrupt */
350: long vddcstat; /* VDDC status */
351: } fmt_mdcb;
352:
353:
354: typedef struct {
355: fmt_mdcb *cdr_mdcb_ptr; /* pointer to controllers mdcb */
356: unsigned long cdr_reset; /* writes here resets controller */
357: unsigned long cdr_csr; /* control / status register */
358: long cdr_reserved; /* don't use */
359: unsigned short cdr_status[16]; /* one status register for each drive */
360: unsigned short stat_chng; /* status change interupt field */
361: unsigned short done_icf; /* done interupt control field */
362: unsigned short error_icf; /* error interupt control field */
363: unsigned short success_icf; /* success interupt control field */
364: unsigned short mdcb_tcf; /* mdcb transfer control field */
365: unsigned short dcb_tcf; /* dcb transfer control field */
366: unsigned short trail_tcf; /* trail transfer control field */
367: unsigned short data_tcf; /* data transfer control field */
368: unsigned long cdr_ccf; /* controller configuration flags */
369: unsigned long sec_size; /* drive sector size */
370: unsigned long diag_flags; /* diagnostic flag register */
371: unsigned long diag_dump; /* pointer for diagnostic addresses */
372: } cdr;
373:
374: /* possible controller types */
375:
376: #define UNKNOWN -1
377: #define SMDCTLR 1
378: #define SMD_ECTLR 2
379:
380: /* the total # of drive types possible */
381:
382: #define XSD 0
383: #define FUJ 1
384: #define XFD 2
385: #define SMD 3
386: #define FSD 4
387:
388:
389: typedef struct {
390: long par_start;
391: long par_len;
392: } par_tab;
393:
394:
395: typedef struct {
396: int secsize; /* Number of bytes in a sector */
397: int nsec; /* Number of sectors per track */
398: int ntrak; /* Number of tracks per cylinder */
399: int ncyl; /* Number of cylinders */
400: int nslip; /* Number of slip sectors */
401: int rpm; /* Revs Per Minute */
402: int nbits; /* Number of bits per track */
403: char *type_name; /* Name of drive */
404: long fmt_pat[16]; /* Patterns to be used for formatting */
405: par_tab partition[8]; /* partition a (root file system) */
406: /* partition b (swap) */
407: /* partition c (user data) */
408: /* partition d (maintenance cyls) */
409: /* partition e (all user data area) */
410: /* partition f ('b' and 'c' combined */
411: /* partition g (1st half of 'c') */
412: /* partition h (2nd half of 'c') */
413: } fs_tab;
414:
415: /* Physical information for known disk drives. */
416: #ifdef VDGENDATA
417: long vddcaddr[] = { 0xf2000, 0xf2100, 0xf2200, 0xf2300 };
418: long vdtimeout = 0;
419:
420: fs_tab vdst[] = {
421: {512, 48, 24, 711, 0, 3600, 0, "xsd", /* 515 Mb FSD */
422: { 0x0264c993, 0x04c99326, 0x0993264c, 0x13264c98,
423: 0x264c9930, 0x4c993260, 0x993264c0, 0x3264c980,
424: 0x64c99300, 0xc9932600, 0x93264c00, 0x264c9800,
425: 0x4c993000, 0x99326000, 0x3264c000, 0x54c98000},
426: {{0, 30528}, /* xsd0a cyl 0 - 52 */
427: {30528, 30528}, /* xsd0b cyl 53 - 105 */
428: {61056, 345600}, /* xsd0c cyl 106 - 705 */
429: {0, 61056}, /* xsd0d cyl 709 - 710 (a & b) */
430: {0, 406656}, /* xsd0e cyl 0 - 705 */
431: {30528, 376128}, /* xsd0f cyl 53 - 705 (b & c) */
432: {61056, 172800}, /* xsd0g cyl 106 - 405 (1/2 of c) */
433: {233856, 172800}} /* xsd0h cyl 406 - 705 (1/2 of c) */
434: },
435: {512, 64, 10, 823, 0, 3600, 0, "fuj", /* 360 Mb Fujitsu */
436: { 0x0264c993, 0x04c99326, 0x0993264c, 0x13264c98,
437: 0x264c9930, 0x4c993260, 0x993264c0, 0x3264c980,
438: 0x64c99300, 0xc9932600, 0x93264c00, 0x264c9800,
439: 0x4c993000, 0x99326000, 0x3264c000, 0x54c98000},
440: {{0, 19200}, /* fuj0a cyl 0 - 59 */
441: {19200, 24000}, /* fuj0b cyl 60 - 134 */
442: {43200, 218560}, /* fuj0c cyl 135 - 817 */
443: {0, 43200}, /* fuj0d cyl 821 - 822 (a & b) */
444: {0, 261760}, /* fuj0e cyl 0 - 817 */
445: {19200, 242560}, /* fuj0f cyl 0 - 134 (b & c) */
446: {43200, 109440}, /* fuj0g cyl 135 - 476 (1/2 of c) */
447: {152640, 109120}} /* fug0h cyl 477 - 817 (1/2 of c) */
448: },
449: {512, 32, 24, 711, 0, 3600, 0, "xfd", /* 340 Mb FSD */
450: { 0x0d9b366c, 0x1b366cd8, 0x366cd9b0, 0x6cd9b360,
451: 0xd9b366c0, 0xb366cd80, 0x66cd9b00, 0xcd9b3600,
452: 0x9b366300, 0x366cd800, 0x6cd9b000, 0xd9b36000,
453: 0xb366c000, 0x66cd8000, 0xcd9b0000, 0x9b360000},
454: {{0, 20352}, /* xfd0a cyl 0 - 52 */
455: {20352, 20352}, /* xfd0b cyl 53 - 105 */
456: {40704, 230400}, /* xfd0c cyl 106 - 705 */
457: {0, 40704}, /* xfd0d cyl 709 - 710 (a & b) */
458: {0, 271104}, /* xfd0e cyl 0 - 705 */
459: {20352, 250752}, /* xfd0f cyl 53 - 705 (b & c) */
460: {40704, 115200}, /* xfd0g cyl 106 - 405 (1/2 of c) */
461: {155904, 115200}} /* xfd0h cyl 406 - 705 (1/2 of c) */
462: },
463: {512, 32, 19, 823, 0, 3600, 0, "smd", /* 300 Mb SMD */
464: { 0x0d9b366c, 0x1b366cd8, 0x366cd9b0, 0x6cd9b360,
465: 0xd9b366c0, 0xb366cd80, 0x66cd9b00, 0xcd9b3600,
466: 0x9b366300, 0x366cd800, 0x6cd9b000, 0xd9b36000,
467: 0xb366c000, 0x66cd8000, 0xcd9b0000, 0x9b360000},
468: {{0, 20064}, /* smd0a cyl 0 - 65 */
469: {20064, 13680}, /* smd0b cyl 66 - 110 */
470: {33744, 214928}, /* smd0c cyl 111 - 817 */
471: {0, 33744}, /* smd0d cyl 0 - 110 (a & b) */
472: {0, 248672}, /* smd0e cyl 0 - 817 */
473: {20064, 228608}, /* smd0f cyl 66 - 817 (b & c) */
474: {33744, 107312}, /* smd0g cyl 111 - 463 (1/2 of c) */
475: {141056, 107616}} /* smd0h cyl 464 - 817 (1/2 of c) */
476: },
477: {512, 32, 10, 823, 0, 3600, 0, "fsd", /* 160 Mb FSD */
478: { 0x0d9b366c, 0x1b366cd8, 0x366cd9b0, 0x6cd9b360,
479: 0xd9b366c0, 0xb366cd80, 0x66cd9b00, 0xcd9b3600,
480: 0x9b366300, 0x366cd800, 0x6cd9b000, 0xd9b36000,
481: 0xb366c000, 0x66cd8000, 0xcd9b0000, 0x9b360000},
482: {{0, 9600}, /* fsd0a cyl 0 - 59 */
483: {9600, 12000}, /* fsd0b cyl 60 - 134 */
484: {21600, 109280}, /* fsd0c cyl 135 - 817 */
485: {0, 21600}, /* fsd0d cyl 0 - 134 (a & b) */
486: {0, 130880}, /* fsd0e cyl 0 - 817 */
487: {9600, 121280}, /* fsd0f cyl 60 - 817 (b & c) */
488: {21600, 54240}, /* fsd0g cyl 135 - 473 (1/2 of c) */
489: {75840, 55040}} /* fsd0h cyl 474 - 817 (1/2 of c) */
490: }
491: };
492:
493: int nvddrv = (sizeof(vdst)/sizeof(fs_tab));
494:
495: #else
496:
497: #ifdef STANDALONE
498:
499: extern long vddcaddr[];
500: extern long vdtimeout;
501: extern fs_tab vdst[];
502: extern int nvddrv;
503:
504: #endif
505:
506: #endif VDGENDATA
507:
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