![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to vddc.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / sys / vba|
Return to vddc.h CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / sys / vba |
Power 6/32 Unix version 1.21
/*
** Header file for the VDDC (Versabus Direct Disk Controller) Driver
*/
/*
** DCB Command Codes
*/
#define RD 0x80 /* Read Data */
#define FTR 0xc0 /* Full Track Read */
#define RAS 0x90 /* Read and Scatter */
#define RD_RAW 0x600 /* Read unformatted disk sector */
#define CMP 0xa0 /* Compare */
#define FTC 0xe0 /* Full Track Compare */
#define RHDE 0x180 /* Read Header, Data & ECC (not used) */
#define WD 0x00 /* Write Data */
#define FTW 0x40 /* Full Track Write */
#define WTC 0x20 /* Write Then Compare */
#define FTWTC 0x60 /* Full Track Write Then Compare */
#define GAW 0x10 /* Gather and Write */
#define WDE 0x100 /* Write Data & ECC (not used) */
#define FSECT 0x900 /* Format Sector */
#define GWC 0x30 /* Gather Write & Compare */
#define VDSTART 0x800 /* Start drives */
#define VDRELEASE 0xa00 /* Stop drives */
#define SEEK 0xb00 /* Seek */
#define INIT 0xc00 /* Initialize VDDC */
#define DIAG 0xd00 /* Diagnose (self-test) VDDC */
#define RSTCFG 0xe00 /* Reset/Configure VDDC/DDI/Drive(s) */
#define VDSTATUS 0xf00 /* VDDC Status */
#define ABORT 0x80000000 /* ABORT active i/o */
/*
** Error / Status Symbolic Constants
*/
#define HCRCERR 0x1 /* Header CRC Error */
#define HCMPERR 0x2 /* Header Compare Error */
#define WPTERR 0x4 /* Write Protect Error/Status */
#define CTLRERR 0x8 /* Controller Error */
#define DSEEKERR 0x10 /* Disk Seek Error */
#define UCDATERR 0x20 /* Uncorrectable Data Error */
#define NOTCYLERR 0x40 /* Not on Cylinder Error */
#define DRVNRDY 0x80 /* Drive Not Ready Error/Status */
#define ALTACC 0x100 /* Alternate (track) accessed Status */
#define SEEKSTRT 0x200 /* Seek Started Status */
#define INVDADR 0x400 /* Invalid Disk Address Error */
#define DNEMEM 0x800 /* Non-Existant Memory Error */
#define PARERR 0x1000 /* Memory Parity Error */
#define DCOMPERR 0x2000 /* Data Compare Error */
#define DDIRDY 0x4000 /* DDI Ready Error/Status */
#define OPABRT 0x8000 /* Operator Abort (Host) Error/Status */
#define DSERLY 0x10000 /* Data Strobe Early */
#define DSLATE 0x20000 /* Data Strobe Late */
#define TOPLUS 0x40000 /* Track Offset Plus */
#define TOMNUS 0x80000 /* Track Offset Minus */
#define CPDCRT 0x100000 /* Cntlr Performed Data Correction */
#define HRDERR 0x200000 /* Hard Error */
#define SFTERR 0x400000 /* Soft Error (retry succesful) */
#define ANYERR 0x800000 /* Any Error */
#define INVCMD 0x1000000 /* Programmer error */
/*
** DCB Status Symbolic Constants
*/
#define DCBABT 0x10000000 /* DCB Aborted */
#define DCBUSC 0x20000000 /* DCB Unsuccesfully Completed */
#define DCBCMP 0x40000000 /* DCB Complete */
#define DCBSTR 0x80000000 /* DCB Started */
/*
** MDCB Status Symbolic Constants
*/
#define CTLRBSY 0x10000000 /* Cntlr Busy */
#define INTCCDE 0x60000000 /* Interrupt Cause Code */
#define DCBINT 0x80000000 /* DCB Interrupt Flag */
/*
** Hard Error Types
*/
#define HTYPES (HCRCERR|HCMPERR|WPTERR|CTLRERR|DSEEKERR|UCDATERR|NOTCYLERR| \
DRVNRDY|INVDADR|DNEMEM|PARERR|DCOMPERR)
/*
** Errors
*/
#define ERRS 0x3FFF
#define CANRETRY (CTLRERR|DSEEKERR|NOTCYLERR|DCOMPERR|UCDATERR| \
PARERR|DNEMEM|HCRCERR|HCMPERR)
/*
** VDDC Interrupt Modes
*/
#define NOINT 0x0 /* No Interrupt */
#define INTERR 0x2 /* Interrupt on Error */
#define INTSUC 0x1 /* Interrupt on Success */
#define INTDONE 0x3 /* Interrupt on Error or Success */
/* Control and Status bit assignments */
#define CS_SCS 0xf /* Status Change Source (drive number) */
#define CS_ELC 0x10 /* Error on Last Command */
#define CS_ICC 0x60 /* Interupt Cause Code */
#define ICC_NOI 0x00 /* No interupt */
#define ICC_DUN 0x20 /* No interupt */
#define ICC_ERR 0x40 /* No interupt */
#define ICC_SUC 0x60 /* No interupt */
#define CS_GO 0x80 /* Go bit (controller working) */
#define CS_BE 0x100 /* Buss Error */
#define CS_BOK 0x4000 /* Board O.K. */
#define CS_SFL 0x8000 /* System fail */
#define CS_LEC 0xff000000 /* Last Error Code */
/* Status word bit assignments */
#define STA_UR 0x1 /* Unit Ready */
#define STA_OC 0x2 /* On Cylinder */
#define STA_SE 0x4 /* Seek Error */
#define STA_DF 0x8 /* Drive Fault */
#define STA_WP 0x10 /* Write Protected */
#define STA_US 0x20 /* Unit Selected */
/* Interupt Control Field bit assignments */
#define ICF_IPL 0x7 /* Interupt Priority Level */
#define ICF_IEN 0x8 /* Interupt ENable */
#define ICF_IV 0xff00 /* Interupt Vector */
/* Transfer Control Format bit assignments */
#define TCF_AM 0xff /* Address Modifier */
#define AM_SNPDA 0x01 /* Standard Non-Privileged Data Access */
#define AM_SASA 0x81 /* Standard Ascending Sequential Access */
#define AM_ENPDA 0xf1 /* Extended Non-Privileged Data Access */
#define AM_EASA 0xe1 /* Extended Ascending Sequential Access */
#define TCF_BTE 0x800 /* Block Transfer Enable */
/* Controller Configuration Flags bit assignments */
#define CCF_STS 0x1 /* Sectors per Track Selectable */
#define CCF_EAV 0x2 /* Enable Auto Vector */
#define CCF_ERR 0x4 /* Enable Reset Register */
#define CCF_DER 0x8 /* Disable Error Recovery */
#define CCF_XMD 0x60 /* XMD transfer mode (buss size) */
#define XMD_8BIT 0x20 /* Do only 8 bit transfers */
#define XMD_16BIT 0x40 /* Do only 16 bit transfers */
#define XMD_32BIT 0x60 /* Do only 32 bit transfers */
#define CCF_BSZ 0x300 /* Burst SiZe */
#define BSZ_16WRD 0x000 /* 16 word transfer burst */
#define BSZ_12WRD 0x100 /* 12 word transfer burst */
#define BSZ_8WRD 0x200 /* 8 word transfer burst */
#define BSZ_4WRD 0x300 /* 4 word transfer burst */
#define CCF_SEN 0x400 /* Cylinder / track Skew ENable (for format) */
#define CCF_ENP 0x1000 /* ENable Parity */
#define CCF_EPE 0x2000 /* Enable Parity Errors */
#define CCF_EDE 0x10000 /* Error Detection Enable */
#define CCF_ECE 0x20000 /* Error Correction Enable */
/* Diagnostic register definitions */
#define DIA_DC 0x7f /* Dump count mask */
#define DIA_DWR 0x80 /* Dump Write / Read flag */
#define DIA_ARE 0x100 /* Auto Rebuild Enable */
#define DIA_CEN 0x200 /* Call ENable flag */
#define DIA_KEY 0xAA550000 /* Reset KEY */
/* Sector Header bit assignments */
#define VDMF 0x8000 /* Manufacturer Fault 1=good sector */
#define VDUF 0x4000 /* User Fault 1=good sector */
#define VDALT 0x2000 /* Alternate Sector 1=alternate */
#define VDWPT 0x1000 /* Write Protect 1=Read Only Sector */
/* DCB Bit assignments */
#define INT_IC 0x3 /* Interupt Control */
#define IC_NOI 0x0 /* NO Interupt */
#define IC_IOD 0x1 /* Interupt On Done */
#define IC_IOE 0x2 /* Interupt On Error */
#define IC_IOS 0x3 /* Interupt On Success */
#define INT_PBA 0x4 /* Proceed before ACK */
/*
** Flaw map stuff
*/
typedef struct {
long flaw_sync;
short flaw_cyl;
char flaw_trk;
char flaw_sec;
struct {
short flaw_offset;
short flaw_length;
} flaw_pos[4];
char flaw_status;
char flaw_junk[1024]; /* Fill up 518 byte block */
} flaw;
typedef struct {
long smde_sync;
unsigned adr_cyl : 12;
unsigned adr_trk : 8;
unsigned adr_sec : 8;
unsigned sec_flgs : 4;
unsigned alt_cyl : 12;
unsigned alt_trk : 8;
unsigned alt_sec : 8;
char smde_junk[1024];
} smde_hdr;
#define CDCSYNC 0x1919
#define SMDSYNC 0x0019
#define SMDESYNC 0x0009
#define SMDE1SYNC 0x000d
/*
** Address of Memory-Mapped I/O Port for VDDC H/W Reset
*/
#define VDDC_RESET(addr, type) { if(type == SMD_ECTLR) { \
(addr)->diag_flags=DIA_KEY | DIA_CEN; \
(addr)->cdr_mdcb_ptr = \
(fmt_mdcb *)0xffffffff; \
DELAY(5000000); \
} \
else { \
(addr)->cdr_reset = 0x0; \
DELAY(1500000); \
} \
}
/*
** Abort controller operation.
*/
#define VDDC_ABORT(a, type) { if((type) == SMDCTLR) { \
movow((int)((ABORT & 0xffff0000)>>16), \
(int)(a)) ; \
movow((int)(ABORT & 0xffff), \
(int)((int)(a)+2)); \
} \
else (a)->cdr_mdcb_ptr = (fmt_mdcb *)ABORT; \
DELAY(1000000); }
/*
** Start i/o to/from controller.
*/
#define VDDC_ATTENTION(ctlr, mdcbadr, type) \
{ if(type == SMDCTLR) { \
movow((int)(((int)mdcbadr & 0xffff0000)>>16), \
(int)ctlr) ; \
movow((int)((int)mdcbadr&0xffff), \
(int)((int)(ctlr)+2)); \
} \
else (ctlr)->cdr_mdcb_ptr = mdcbadr; }
#define POLLTILLDONE(c, a, x, t) { vdtimeout = 1000*(x); \
uncache(&((a)->operrsta)); \
while (!(((a)->operrsta) & (DCBCMP | DCBABT))) { \
DELAY(1000); \
vdtimeout--; \
uncache(&((a)->operrsta)); \
if (vdtimeout <= 0) { \
printf("VDDC: Controller timeout"); \
VDDC_ABORT(c, t); \
DELAY(30000); \
break; \
} \
} \
if((vdtimeout > 0)) \
if((t == SMD_ECTLR) && (vdtimeout > 0)) { \
uncache(&(c)->cdr_csr); \
while((c)->cdr_csr & CS_GO) { \
DELAY(50); \
uncache(&(c)->cdr_csr); \
} \
DELAY(500); \
} \
else DELAY(200); \
uncache(&((a)->operrsta)); \
}
/* Disk Address */
typedef struct {
char track; /* all 8 bits */
char sector; /* all 8 bits */
short cylinder; /* low order 12 bits */
} dskadr;
/* sector formats */
typedef union {
struct {
dskadr hdr_addr;
short smd_crc;
} smd;
struct {
dskadr physical;
dskadr logical;
long smd_e_crc;
} smd_e;
} fmt_hdr;
/* DCB Trailer Formats */
/* Read / Write Trailer */
typedef struct {
char *memadr; /* memory address */
unsigned long wcount; /* 16 bit word count */
dskadr disk; /* disk address */
} trrw;
/* Scatter/gather trailer */
typedef struct {
trrw start_addr;
struct {
char *nxt_addr;
unsigned long nxt_len;
} addr_chain[126];
} trsg;
/* Seek trailer format */
typedef struct {
dskadr skaddr;
} trseek;
/* Format Trailer */
typedef struct {
char *addr; /* data buffer to be filled on sector*/
long nsectors; /* # of sectors to be formatted */
dskadr disk; /* Disk physical address info */
dskadr hdr; /* Header address info */
} trfmt;
/* Reset / Configure Trailer */
typedef struct {
long ncyl; /* # cylinders */
long nsurfaces; /* # surfaces */
long nsectors; /* # sectors */
long slip_sec; /* # of slip sectors */
long recovery; /* Recovery flags */
} treset;
/* DCB Format */
typedef struct fmtdcb{
struct fmtdcb *nxtdcb; /* next dcb in chain or End of Chain */
short intflg; /* interrupt settings and flags */
short opcode; /* DCB Command code etc... */
long operrsta; /* Error & Status info */
short fill; /* not used */
char devselect; /* Drive selection */
char trailcnt; /* Trailer Word Count */
long err_memadr; /* Error memory address */
char err_code; /* Error codes for SMD/E */
char fill2; /* not used */
short err_wcount; /* Error word count */
char err_trk; /* Error track/sector */
char err_sec; /* Error track/sector */
short err_cyl; /* Error cylinder adr */
union {
trseek sktrail; /* seek command trailer */
trsg sgtrail; /* Scatter gather trailer */
trrw rwtrail; /* read/write trailer */
trfmt fmtrail; /* format trailer */
treset rstrail; /* reset/configure trailer */
} trail;
} fmt_dcb;
/* MDCB Format */
typedef struct {
fmt_dcb *firstdcb; /* first dcb in chain */
fmt_dcb *procdcb; /* dcb being processed */
fmt_dcb *intdcb; /* dcb causing interrupt */
long vddcstat; /* VDDC status */
} fmt_mdcb;
typedef struct {
fmt_mdcb *cdr_mdcb_ptr; /* pointer to controllers mdcb */
unsigned long cdr_reset; /* writes here resets controller */
unsigned long cdr_csr; /* control / status register */
long cdr_reserved; /* don't use */
unsigned short cdr_status[16]; /* one status register for each drive */
unsigned short stat_chng; /* status change interupt field */
unsigned short done_icf; /* done interupt control field */
unsigned short error_icf; /* error interupt control field */
unsigned short success_icf; /* success interupt control field */
unsigned short mdcb_tcf; /* mdcb transfer control field */
unsigned short dcb_tcf; /* dcb transfer control field */
unsigned short trail_tcf; /* trail transfer control field */
unsigned short data_tcf; /* data transfer control field */
unsigned long cdr_ccf; /* controller configuration flags */
unsigned long sec_size; /* drive sector size */
unsigned short cdr_unused0;
unsigned char cyl_skew; /* cylinder to cylinder skew factor */
unsigned char trk_skew; /* track to track skew factor */
unsigned long cdr_unused1;
unsigned long diag_flags; /* diagnostic flag register */
unsigned long diag_dump; /* pointer for diagnostic addresses */
} cdr;
/* possible controller types */
#define UNKNOWN -1
#define SMDCTLR 1
#define SMD_ECTLR 2
/* the total # of drive types possible */
#define XSD 0
#define FUJ 1
#define XFD 2
#define SMD 3
#define FSD 4
typedef struct {
long par_start;
long par_len;
} par_tab;
typedef struct {
int secsize; /* Number of bytes in a sector */
int nsec; /* Number of sectors per track */
int ntrak; /* Number of tracks per cylinder */
int ncyl; /* Number of cylinders */
int nslip; /* Number of slip sectors */
int rpm; /* Revs Per Minute */
int nbyte; /* Number of bits per track */
char *type_name; /* Name of drive */
char *type_discript; /* discriptition of drive */
long fmt_pat[16]; /* Patterns to be used for formatting */
par_tab partition[8]; /* partition a (root file system) */
/* partition b (swap) */
/* partition c (user data) */
/* partition d (maintenance cyls) */
/* partition e (all user data area) */
/* partition f ('b' and 'c' combined */
/* partition g (1st half of 'c') */
/* partition h (2nd half of 'c') */
} fs_tab;
/* Physical information for known disk drives. */
#ifdef VDGENDATA
long vddcaddr[] = { 0xf2000, 0xf2100, 0xf2200, 0xf2300,
0xf2400, 0xf2500, 0xf2600, 0xf2700 };
long vdtimeout = 0;
fs_tab vdst[] = {
{512, 48, 24, 711, 0, 3600, 30240, "xsd",
"515 Mb Control Data Winchester drive",
{ 0x0264c993, 0x04c99326, 0x0993264c, 0x13264c98,
0x264c9930, 0x4c993260, 0x993264c0, 0x3264c980,
0x64c99300, 0xc9932600, 0x93264c00, 0x264c9800,
0x4c993000, 0x99326000, 0x3264c000, 0x54c98000},
{{0, 30528}, /* xsd0a cyl 0 - 52 */
{30528, 30528}, /* xsd0b cyl 53 - 105 */
{61056, 345600}, /* xsd0c cyl 106 - 705 */
{118656, 288000}, /* xsd0d cyl 206 - 705 */
{176256, 230400}, /* xsd0e cyl 306 - 705 */
{233856, 172800}, /* xsd0f cyl 406 - 705 */
{291456, 115200}, /* xsd0g cyl 506 - 705 */
{349056, 57600}} /* xsd0h cyl 606 - 705 */
},
{512, 66, 23, 850, 0, 3600, 40960, "ncc",
"800Mb NEC",
{ 0x0264c993, 0x04c99326, 0x0993264c, 0x13264c98,
0x264c9930, 0x4c993260, 0x993264c0, 0x3264c980,
0x64c99300, 0xc9932600, 0x93264c00, 0x264c9800,
0x4c993000, 0x99326000, 0x3264c000, 0x54c98000},
{{0, 26400}, /* egl0a */
{26400, 33000}, /* egl0b */
{59400, 308880}} /* egl0c */
},
{512, 44, 20, 842, 0, 3600, 27720, "egl",
"474 Mb Fujitsu Eagle drive",
{ 0x0264c993, 0x04c99326, 0x0993264c, 0x13264c98,
0x264c9930, 0x4c993260, 0x993264c0, 0x3264c980,
0x64c99300, 0xc9932600, 0x93264c00, 0x264c9800,
0x4c993000, 0x99326000, 0x3264c000, 0x54c98000},
{{0, 26400}, /* egl0a */
{26400, 33000}, /* egl0b */
{59400, 308880}} /* egl0c */
},
{512, 64, 10, 823, 0, 3600, 40960, "fuj", /* 360 Mb Fujitsu */
"360 Mb Fujitsu Winchester drive",
{ 0x0264c993, 0x04c99326, 0x0993264c, 0x13264c98,
0x264c9930, 0x4c993260, 0x993264c0, 0x3264c980,
0x64c99300, 0xc9932600, 0x93264c00, 0x264c9800,
0x4c993000, 0x99326000, 0x3264c000, 0x54c98000},
{{0, 19200}, /* fuj0a cyl 0 - 59 */
{19200, 24000}, /* fuj0b cyl 60 - 134 */
{43200, 218560}, /* fuj0c cyl 135 - 817 */
{79680, 182080}, /* fuj0d cyl 249 - 817 */
{116160, 145600}, /* fuj0e cyl 363 - 817 */
{152640, 109120}, /* fuj0f cyl 477 - 817 */
{189120, 72640}, /* fuj0g cyl 591 - 817 */
{225600, 36160}} /* fug0h cyl 705 - 817 */
},
{512, 32, 24, 711, 0, 3600, 20160, "xfd", /* 340 Mb FSD */
"340 Mb Control Data Winchester drive",
{ 0x0d9b366c, 0x1b366cd8, 0x366cd9b0, 0x6cd9b360,
0xd9b366c0, 0xb366cd80, 0x66cd9b00, 0xcd9b3600,
0x9b366300, 0x366cd800, 0x6cd9b000, 0xd9b36000,
0xb366c000, 0x66cd8000, 0xcd9b0000, 0x9b360000},
{{0, 20352}, /* xfd0a cyl 0 - 52 */
{20352, 20352}, /* xfd0b cyl 53 - 105 */
{40704, 230400}, /* xfd0c cyl 106 - 705 */
{79104, 192000}, /* xfd0d cyl 206 - 705 */
{117504, 153600}, /* xfd0e cyl 306 - 705 */
{155904, 115200}, /* xfd0f cyl 406 - 705 */
{194304, 76800}, /* xfd0g cyl 506 - 705 */
{232704, 38400}} /* xfd0h cyl 606 - 705 */
},
{512, 32, 19, 823, 0, 3600, 20160, "smd", /* 300 Mb SMD */
"300 Mb Control Data removable media drive",
{ 0x0d9b366c, 0x1b366cd8, 0x366cd9b0, 0x6cd9b360,
0xd9b366c0, 0xb366cd80, 0x66cd9b00, 0xcd9b3600,
0x9b366300, 0x366cd800, 0x6cd9b000, 0xd9b36000,
0xb366c000, 0x66cd8000, 0xcd9b0000, 0x9b360000},
{{0, 20064}, /* smd0a cyl 0 - 65 */
{20064, 13680}, /* smd0b cyl 66 - 110 */
{33744, 214928}, /* smd0c cyl 111 - 817 */
{69616, 179056}, /* smd0d cyl 229 - 817 */
{105488, 143184}, /* smd0e cyl 347 - 817 */
{141360, 107312}, /* smd0f cyl 465 - 817 */
{177232, 71440}, /* smd0g cyl 583 - 817 */
{213104, 35568}} /* smd0h cyl 701 - 817 */
},
{512, 32, 10, 823, 0, 3600, 20160, "fsd", /* 160 Mb FSD */
"160 Mb Control Data Winchester drive",
{ 0x0d9b366c, 0x1b366cd8, 0x366cd9b0, 0x6cd9b360,
0xd9b366c0, 0xb366cd80, 0x66cd9b00, 0xcd9b3600,
0x9b366300, 0x366cd800, 0x6cd9b000, 0xd9b36000,
0xb366c000, 0x66cd8000, 0xcd9b0000, 0x9b360000},
{{0, 9600}, /* fsd0a cyl 0 - 59 */
{9600, 12000}, /* fsd0b cyl 60 - 134 */
{21600, 109280}, /* fsd0c cyl 135 - 817 */
{39840, 91040}, /* fsd0d cyl 249 - 817 */
{58080, 72800}, /* fsd0e cyl 363 - 817 */
{76320, 54560}, /* fsd0f cyl 477 - 817 */
{94560, 36320}, /* fsd0g cyl 591 - 817 */
{112800, 18080}} /* fsd0h cyl 705 - 817 */
}
};
int nvddrv = (sizeof(vdst)/sizeof(fs_tab));
#else
extern long vddcaddr[];
extern long vdtimeout;
extern fs_tab vdst[];
extern int nvddrv;
#endif VDGENDATA
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.