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1.1 root 1: /*
2: * Cisco 7200 (Predator) simulation platform.
3: * Copyright (c) 2005,2006 Christophe Fillot ([email protected])
4: */
5:
6: #ifndef __MIPS_64_H__
7: #define __MIPS_64_H__
8:
9: #include <pthread.h>
10:
11: #include "utils.h"
12: #include "rbtree.h"
13:
1.1.1.4 root 14: /*
15: * MIPS General Purpose Registers
16: */
17: #define MIPS_GPR_ZERO 0 /* zero */
18: #define MIPS_GPR_AT 1 /* at */
19: #define MIPS_GPR_V0 2 /* v0 */
20: #define MIPS_GPR_V1 3 /* v1 */
21: #define MIPS_GPR_A0 4 /* a0 */
22: #define MIPS_GPR_A1 5 /* a1 */
23: #define MIPS_GPR_A2 6 /* a2 */
24: #define MIPS_GPR_A3 7 /* a3 */
25: #define MIPS_GPR_T0 8 /* t0 */
26: #define MIPS_GPR_T1 9 /* t1 */
27: #define MIPS_GPR_T2 10 /* t2 */
28: #define MIPS_GPR_T3 11 /* t3 */
29: #define MIPS_GPR_T4 12 /* t4 */
30: #define MIPS_GPR_T5 13 /* t5 */
31: #define MIPS_GPR_T6 14 /* t6 */
32: #define MIPS_GPR_T7 15 /* t7 */
33: #define MIPS_GPR_S0 16 /* s0 */
34: #define MIPS_GPR_S1 17 /* s1 */
35: #define MIPS_GPR_S2 18 /* s2 */
36: #define MIPS_GPR_S3 19 /* s3 */
37: #define MIPS_GPR_S4 20 /* s4 */
38: #define MIPS_GPR_S5 21 /* s5 */
39: #define MIPS_GPR_S6 22 /* s6 */
40: #define MIPS_GPR_S7 23 /* s7 */
41: #define MIPS_GPR_T8 24 /* t8 */
42: #define MIPS_GPR_T9 25 /* t9 */
43: #define MIPS_GPR_K0 26 /* k0 */
44: #define MIPS_GPR_K1 27 /* k1 */
45: #define MIPS_GPR_GP 28 /* gp */
46: #define MIPS_GPR_SP 29 /* sp */
47: #define MIPS_GPR_FP 30 /* fp */
48: #define MIPS_GPR_RA 31 /* ra */
1.1 root 49:
50: /*
51: * Coprocessor 0 (System Coprocessor) Register definitions
52: */
1.1.1.4 root 53: #define MIPS_CP0_INDEX 0 /* TLB Index */
54: #define MIPS_CP0_RANDOM 1 /* TLB Random */
55: #define MIPS_CP0_TLB_LO_0 2 /* TLB Entry Lo0 */
56: #define MIPS_CP0_TLB_LO_1 3 /* TLB Entry Lo1 */
57: #define MIPS_CP0_CONTEXT 4 /* Kernel PTE pointer */
58: #define MIPS_CP0_PAGEMASK 5 /* TLB Page Mask */
59: #define MIPS_CP0_WIRED 6 /* TLB Wired */
60: #define MIPS_CP0_INFO 7 /* Info (RM7000) */
61: #define MIPS_CP0_BADVADDR 8 /* Bad Virtual Address */
62: #define MIPS_CP0_COUNT 9 /* Count */
63: #define MIPS_CP0_TLB_HI 10 /* TLB Entry Hi */
64: #define MIPS_CP0_COMPARE 11 /* Timer Compare */
65: #define MIPS_CP0_STATUS 12 /* Status */
66: #define MIPS_CP0_CAUSE 13 /* Cause */
67: #define MIPS_CP0_EPC 14 /* Exception PC */
68: #define MIPS_CP0_PRID 15 /* Proc Rev ID */
69: #define MIPS_CP0_CONFIG 16 /* Configuration */
70: #define MIPS_CP0_LLADDR 17 /* Load/Link address */
71: #define MIPS_CP0_WATCHLO 18 /* Low Watch address */
72: #define MIPS_CP0_WATCHHI 19 /* High Watch address */
73: #define MIPS_CP0_XCONTEXT 20 /* Extended context */
74: #define MIPS_CP0_ECC 26 /* ECC and parity */
75: #define MIPS_CP0_CACHERR 27 /* Cache Err/Status */
76: #define MIPS_CP0_TAGLO 28 /* Cache Tag Lo */
77: #define MIPS_CP0_TAGHI 29 /* Cache Tag Hi */
78: #define MIPS_CP0_ERR_EPC 30 /* Error exception PC */
79:
80: /*
81: * CP0 Set 1 Registers (R7000)
82: */
83: #define MIPS_CP0_S1_CONFIG 16 /* Configuration Register */
84: #define MIPS_CP0_S1_IPLLO 18 /* Priority level for IRQ [7:0] */
85: #define MIPS_CP0_S1_IPLHI 19 /* Priority level for IRQ [15:8] */
86: #define MIPS_CP0_S1_INTCTL 20 /* Interrupt Control */
87: #define MIPS_CP0_S1_DERRADDR0 26 /* Imprecise Error Address */
88: #define MIPS_CP0_S1_DERRADDR1 27 /* Imprecise Error Address */
1.1 root 89:
90: /*
91: * CP0 Status Register
92: */
93: #define MIPS_CP0_STATUS_CU0 0x10000000
94: #define MIPS_CP0_STATUS_CU1 0x20000000
95: #define MIPS_CP0_STATUS_BEV 0x00400000
96: #define MIPS_CP0_STATUS_TS 0x00200000
97: #define MIPS_CP0_STATUS_SR 0x00100000
98: #define MIPS_CP0_STATUS_CH 0x00040000
99: #define MIPS_CP0_STATUS_CE 0x00020000
100: #define MIPS_CP0_STATUS_DE 0x00010000
101: #define MIPS_CP0_STATUS_RP 0x08000000
102: #define MIPS_CP0_STATUS_FR 0x04000000
103: #define MIPS_CP0_STATUS_RE 0x02000000
104: #define MIPS_CP0_STATUS_KX 0x00000080
105: #define MIPS_CP0_STATUS_SX 0x00000040
106: #define MIPS_CP0_STATUS_UX 0x00000020
107: #define MIPS_CP0_STATUS_KSU 0x00000018
108: #define MIPS_CP0_STATUS_ERL 0x00000004
109: #define MIPS_CP0_STATUS_EXL 0x00000002
110: #define MIPS_CP0_STATUS_IE 0x00000001
111: #define MIPS_CP0_STATUS_IMASK7 0x00008000
112: #define MIPS_CP0_STATUS_IMASK6 0x00004000
113: #define MIPS_CP0_STATUS_IMASK5 0x00002000
114: #define MIPS_CP0_STATUS_IMASK4 0x00001000
115: #define MIPS_CP0_STATUS_IMASK3 0x00000800
116: #define MIPS_CP0_STATUS_IMASK2 0x00000400
117: #define MIPS_CP0_STATUS_IMASK1 0x00000200
118: #define MIPS_CP0_STATUS_IMASK0 0x00000100
119:
120: #define MIPS_CP0_STATUS_DS_MASK 0x00770000
121: #define MIPS_CP0_STATUS_CU_MASK 0xF0000000
122: #define MIPS_CP0_STATUS_IMASK 0x0000FF00
123:
124: /* Addressing mode: Kernel, Supervisor and User */
125: #define MIPS_CP0_STATUS_KSU_SHIFT 0x03
126: #define MIPS_CP0_STATUS_KSU_MASK 0x03
127:
128: #define MIPS_CP0_STATUS_KM 0x00
129: #define MIPS_CP0_STATUS_SM 0x01
130: #define MIPS_CP0_STATUS_UM 0x10
131:
132:
133: /*
134: * CP0 Cause register
135: */
136: #define MIPS_CP0_CAUSE_BD_SLOT 0x80000000
137:
138: #define MIPS_CP0_CAUSE_MASK 0x0000007C
139: #define MIPS_CP0_CAUSE_CEMASK 0x30000000
140: #define MIPS_CP0_CAUSE_IMASK 0x0000FF00
141:
142: #define MIPS_CP0_CAUSE_SHIFT 2
143: #define MIPS_CP0_CAUSE_CESHIFT 28
144: #define MIPS_CP0_CAUSE_ISHIFT 8
145:
146: #define MIPS_CP0_CAUSE_INTERRUPT 0
147: #define MIPS_CP0_CAUSE_TLB_MOD 1
148: #define MIPS_CP0_CAUSE_TLB_LOAD 2
149: #define MIPS_CP0_CAUSE_TLB_SAVE 3
150: #define MIPS_CP0_CAUSE_ADDR_LOAD 4 /* ADEL */
151: #define MIPS_CP0_CAUSE_ADDR_SAVE 5 /* ADES */
152: #define MIPS_CP0_CAUSE_BUS_INSTR 6
153: #define MIPS_CP0_CAUSE_BUS_DATA 7
154: #define MIPS_CP0_CAUSE_SYSCALL 8
155: #define MIPS_CP0_CAUSE_BP 9
156: #define MIPS_CP0_CAUSE_ILLOP 10
157: #define MIPS_CP0_CAUSE_CP_UNUSABLE 11
158: #define MIPS_CP0_CAUSE_OVFLW 12
159: #define MIPS_CP0_CAUSE_TRAP 13
160: #define MIPS_CP0_CAUSE_VC_INSTR 14 /* Virtual Coherency */
161: #define MIPS_CP0_CAUSE_FPE 15
162: #define MIPS_CP0_CAUSE_WATCH 23
163: #define MIPS_CP0_CAUSE_VC_DATA 31 /* Virtual Coherency */
164:
165: #define MIPS_CP0_CAUSE_IBIT7 0x00008000
166: #define MIPS_CP0_CAUSE_IBIT6 0x00004000
167: #define MIPS_CP0_CAUSE_IBIT5 0x00002000
168: #define MIPS_CP0_CAUSE_IBIT4 0x00001000
169: #define MIPS_CP0_CAUSE_IBIT3 0x00000800
170: #define MIPS_CP0_CAUSE_IBIT2 0x00000400
171: #define MIPS_CP0_CAUSE_IBIT1 0x00000200
172: #define MIPS_CP0_CAUSE_IBIT0 0x00000100
173:
174:
175: /* TLB masks and shifts */
176: #define MIPS_TLB_PAGE_MASK 0x01ffe000
177: #define MIPS_TLB_PAGE_SHIFT 13
1.1.1.7 ! root 178: #define MIPS_TLB_VPN2_MASK_32 0xffffe000ULL
! 179: #define MIPS_TLB_VPN2_MASK_64 0xc00000ffffffe000ULL
1.1 root 180: #define MIPS_TLB_PFN_MASK 0x3fffffc0
1.1.1.4 root 181: #define MIPS_TLB_ASID_MASK 0x000000ff /* "asid" in EntryHi */
182: #define MIPS_TLB_G_MASK 0x00001000 /* "Global" in EntryHi */
183: #define MIPS_TLB_V_MASK 0x2 /* "Valid" in EntryLo */
184: #define MIPS_TLB_D_MASK 0x4 /* "Dirty" in EntryLo */
185: #define MIPS_TLB_C_MASK 0x38 /* Page Coherency Attribute */
186: #define MIPS_TLB_C_SHIFT 3
1.1 root 187:
188: #define MIPS_CP0_LO_G_MASK 0x00000001 /* "Global" in Lo0/1 reg */
189: #define MIPS_CP0_HI_SAFE_MASK 0xffffe0ff /* Safety mask for Hi reg */
190: #define MIPS_CP0_LO_SAFE_MASK 0x7fffffff /* Safety mask for Lo reg */
191:
192: /* MIPS "jr ra" instruction */
1.1.1.4 root 193: #define MIPS_INSN_JR_RA 0x03e00008
1.1 root 194:
195: /* Minimum page size: 4 Kb */
1.1.1.4 root 196: #define MIPS_MIN_PAGE_SHIFT 12
197: #define MIPS_MIN_PAGE_SIZE (1 << MIPS_MIN_PAGE_SHIFT)
198: #define MIPS_MIN_PAGE_IMASK (MIPS_MIN_PAGE_SIZE - 1)
1.1 root 199:
200: /* Addressing mode: Kernel, Supervisor and User */
201: #define MIPS_MODE_KERNEL 00
202:
203: /* Segments in 32-bit User mode */
204: #define MIPS_USEG_BASE 0x00000000
205: #define MIPS_USEG_SIZE 0x80000000
206:
207: /* Segments in 32-bit Supervisor mode */
208: #define MIPS_SUSEG_BASE 0x00000000
209: #define MIPS_SUSEG_SIZE 0x80000000
210: #define MIPS_SSEG_BASE 0xc0000000
211: #define MIPS_SSEG_SIZE 0x20000000
212:
213: /* Segments in 32-bit Kernel mode */
214: #define MIPS_KUSEG_BASE 0x00000000
215: #define MIPS_KUSEG_SIZE 0x80000000
216:
217: #define MIPS_KSEG0_BASE 0x80000000
218: #define MIPS_KSEG0_SIZE 0x20000000
219:
220: #define MIPS_KSEG1_BASE 0xa0000000
221: #define MIPS_KSEG1_SIZE 0x20000000
222:
223: #define MIPS_KSSEG_BASE 0xc0000000
224: #define MIPS_KSSEG_SIZE 0x20000000
225:
226: #define MIPS_KSEG3_BASE 0xe0000000
227: #define MIPS_KSEG3_SIZE 0x20000000
228:
1.1.1.4 root 229: /* xkphys mask (36-bit physical address) */
230: #define MIPS64_XKPHYS_ZONE_MASK 0xF800000000000000ULL
231: #define MIPS64_XKPHYS_PHYS_SIZE (1ULL << 36)
232: #define MIPS64_XKPHYS_PHYS_MASK (MIPS64_XKPHYS_PHYS_SIZE - 1)
233: #define MIPS64_XKPHYS_CCA_SHIFT 59
234:
1.1 root 235: /* Macros for CPU structure access */
236: #define REG_OFFSET(reg) (OFFSET(cpu_mips_t,gpr[(reg)]))
237: #define CP0_REG_OFFSET(c0reg) (OFFSET(cpu_mips_t,cp0.reg[(c0reg)]))
238: #define MEMOP_OFFSET(op) (OFFSET(cpu_mips_t,mem_op_fn[(op)]))
239:
240: /* Initial Program Counter and Stack pointer for ROM */
241: #define MIPS_ROM_PC 0xffffffffbfc00000ULL
242: #define MIPS_ROM_SP 0xffffffff80004000ULL
243:
244: /* Number of GPR (general purpose registers) */
245: #define MIPS64_GPR_NR 32
246:
247: /* Number of registers in CP0 */
248: #define MIPS64_CP0_REG_NR 32
249:
250: /* Number of registers in CP1 */
251: #define MIPS64_CP1_REG_NR 32
252:
253: /* Number of TLB entries */
1.1.1.4 root 254: #define MIPS64_TLB_STD_ENTRIES 48
255: #define MIPS64_TLB_MAX_ENTRIES 64
256: #define MIPS64_TLB_IDX_MASK 0x3f /* 6 bits */
257:
258: /* Enable the 64 TLB entries for R7000 CPU */
259: #define MIPS64_R7000_TLB64_ENABLE 0x20000000
260:
261: /* MIPS CPU Identifiers */
262: #define MIPS_PRID_R4600 0x00002012
263: #define MIPS_PRID_R4700 0x00002112
264: #define MIPS_PRID_R5000 0x00002312
265: #define MIPS_PRID_R7000 0x00002721
266: #define MIPS_PRID_R527x 0x00002812
267: #define MIPS_PRID_BCM1250 0x00040102
1.1 root 268:
269: /* Virtual CPU states */
270: enum {
271: MIPS_CPU_RUNNING = 0,
272: MIPS_CPU_HALTED,
273: MIPS_CPU_SUSPENDED,
274: };
275:
276: /* Memory operations */
277: enum {
1.1.1.4 root 278: MIPS_MEMOP_LOOKUP = 0,
279:
280: MIPS_MEMOP_LB,
1.1 root 281: MIPS_MEMOP_LBU,
282: MIPS_MEMOP_LH,
283: MIPS_MEMOP_LHU,
284: MIPS_MEMOP_LW,
285: MIPS_MEMOP_LWU,
286: MIPS_MEMOP_LD,
287: MIPS_MEMOP_SB,
288: MIPS_MEMOP_SH,
289: MIPS_MEMOP_SW,
290: MIPS_MEMOP_SD,
291:
292: MIPS_MEMOP_LWL,
293: MIPS_MEMOP_LWR,
294: MIPS_MEMOP_LDL,
295: MIPS_MEMOP_LDR,
296: MIPS_MEMOP_SWL,
297: MIPS_MEMOP_SWR,
298: MIPS_MEMOP_SDL,
299: MIPS_MEMOP_SDR,
300:
301: MIPS_MEMOP_LL,
302: MIPS_MEMOP_SC,
303:
304: MIPS_MEMOP_LDC1,
305: MIPS_MEMOP_SDC1,
306:
307: MIPS_MEMOP_CACHE,
308:
309: MIPS_MEMOP_MAX,
310: };
311:
312: /* 6 bits are reserved for device ID (see the memory subsystem) */
313: #define MIPS64_DEVICE_MAX (1 << 6)
314:
315: /* Number of recorded memory accesses (power of two) */
316: #define MEMLOG_COUNT 16
317:
318: /* Maximum number of breakpoints */
319: #define MIPS64_MAX_BREAKPOINTS 8
320:
321: typedef struct memlog_access memlog_access_t;
322: struct memlog_access {
323: m_uint64_t pc;
324: m_uint64_t vaddr;
325: m_uint64_t data;
326: m_uint32_t data_valid;
327: m_uint32_t op_size;
328: m_uint32_t op_type;
329: };
330:
331: /* MIPS CPU type */
332: typedef struct cpu_mips cpu_mips_t;
333:
334: /* Memory operation function prototype */
335: typedef fastcall u_int (*mips_memop_fn)(cpu_mips_t *cpu,m_uint64_t vaddr,
336: u_int reg);
337:
338: /* TLB entry definition */
339: typedef struct {
340: m_uint64_t mask;
341: m_uint64_t hi;
342: m_uint64_t lo0;
343: m_uint64_t lo1;
344: }tlb_entry_t;
345:
346: /* System Coprocessor (CP0) definition */
347: typedef struct {
348: m_uint64_t reg[MIPS64_CP0_REG_NR];
1.1.1.4 root 349: tlb_entry_t tlb[MIPS64_TLB_MAX_ENTRIES];
350:
351: /* Number of TLB entries */
352: u_int tlb_entries;
353:
354: /* Extensions for R7000 CP0 Set1 */
355: m_uint32_t ipl_lo,ipl_hi,int_ctl;
356: m_uint32_t derraddr0,derraddr1;
1.1 root 357: }mips_cp0_t;
358:
359: /* FPU Coprocessor (CP1) definition */
360: typedef struct {
361: m_uint64_t reg[MIPS64_CP1_REG_NR];
362: }mips_cp1_t;
363:
1.1.1.4 root 364: /* MTS64 entry */
365: typedef struct mts64_entry mts64_entry_t;
366: struct mts64_entry {
367: m_uint64_t start;
368: m_iptr_t action;
369: m_uint32_t mask;
370: m_uint32_t phys_page;
371: mts64_entry_t **pself;
372: mts64_entry_t *next,**pprev;
373: };
1.1 root 374:
1.1.1.7 ! root 375: /* MTS32 entry */
! 376: typedef struct mts32_entry mts32_entry_t;
! 377: struct mts32_entry {
! 378: m_uint32_t start;
! 379: m_iptr_t action;
! 380: m_uint32_t mask;
! 381: m_uint32_t phys_page;
! 382: mts32_entry_t **pself;
! 383: mts32_entry_t *next,**pprev;
! 384: };
! 385:
! 386: /* MTS chunk forward declaration */
1.1.1.4 root 387: typedef struct mts64_chunk mts64_chunk_t;
1.1.1.7 ! root 388: typedef struct mts32_chunk mts32_chunk_t;
1.1.1.2 root 389:
1.1.1.6 root 390: /* Maximum results for idle pc */
391: #define MIPS64_IDLE_PC_MAX_RES 10
392:
393: /* Idle PC hash item */
394: struct mips64_idle_pc {
395: m_uint64_t pc;
396: u_int count;
397: };
398:
1.1.1.4 root 399: /* MIPS CPU definition */
400: struct cpu_mips {
1.1 root 401: /* MTS 1st level array */
402: void *mts_l1_ptr;
403:
1.1.1.7 ! root 404: /* MTS32/MTS64 caches */
! 405: void **mts_cache;
1.1.1.4 root 406:
407: /* Virtual version of CP0 Compare Register */
408: m_uint32_t cp0_virt_cnt_reg,cp0_virt_cmp_reg;
409:
410: /* General Purpose Registers, Pointer Counter, LO/HI, IRQ */
411: m_uint32_t irq_pending,irq_cause,ll_bit;
412: m_uint64_t pc,gpr[MIPS64_GPR_NR];
413: m_uint64_t lo,hi,ret_pc;
1.1 root 414:
1.1.1.4 root 415: /* Code page translation cache */
416: insn_block_t **exec_phys_map;
417:
418: /* Virtual address to physical page translation */
419: fastcall int (*translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
420: m_uint32_t *phys_page);
421:
1.1 root 422: /* Memory access functions */
423: mips_memop_fn mem_op_fn[MIPS_MEMOP_MAX];
424:
1.1.1.4 root 425: /* Memory lookup function (to load ELF image,...) */
426: void *(*mem_op_lookup)(cpu_mips_t *cpu,m_uint64_t vaddr);
1.1 root 427:
428: /* System coprocessor (CP0) */
429: mips_cp0_t cp0;
430:
431: /* FPU (CP1) */
432: mips_cp1_t fpu;
433:
1.1.1.7 ! root 434: /* Address bus mask for physical addresses */
1.1.1.4 root 435: m_uint64_t addr_bus_mask;
436:
437: /* IRQ counters and cause */
438: m_uint64_t irq_count,timer_irq_count,irq_fp_count;
439: pthread_mutex_t irq_lock;
440:
441: /* Current and free lists of instruction blocks */
442: insn_block_t *insn_block_list,*insn_block_last;
443: insn_block_t *insn_block_free_list;
444:
445: /* Executable page area */
446: void *exec_page_area;
447: size_t exec_page_area_size;
448: size_t exec_page_count,exec_page_alloc;
449: insn_exec_page_t *exec_page_free_list;
450: insn_exec_page_t *exec_page_array;
451:
452: /* "Idle" loop management */
453: volatile m_uint64_t idle_pc;
1.1.1.6 root 454: u_int idle_count,idle_max,idle_sleep_time;
1.1.1.4 root 455: pthread_mutex_t idle_mutex;
456: pthread_cond_t idle_cond;
457:
458: /* IRQ disable flag */
459: volatile u_int irq_disable;
460:
461: /* Timer IRQs */
462: volatile u_int timer_irq_pending;
463: u_int timer_irq_freq;
464: u_int timer_irq_check_itv;
465: u_int timer_drift;
466:
467: /* IRQ idling preemption */
468: u_int irq_idle_preempt[8];
469:
470: /* CPU identifier for MP systems */
471: u_int id;
472:
473: /* CPU states */
474: volatile u_int state,prev_state;
475: volatile m_uint64_t seq_state;
1.1 root 476:
477: /* Thread running this CPU */
478: pthread_t cpu_thread;
1.1.1.4 root 479: int cpu_thread_running;
480:
481: /* VM instance */
482: vm_instance_t *vm;
483:
484: /* non-JIT mode instruction counter */
485: m_uint64_t insn_exec_count;
486:
487: /* MTS map/unmap/rebuild operations */
488: void (*mts_map)(cpu_mips_t *cpu,m_uint64_t vaddr,
489: m_uint64_t paddr,m_uint32_t len,
490: int cache_access,int tlb_index);
491:
492: void (*mts_unmap)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t len,
493: m_uint32_t val,int tlb_index);
494:
495: void (*mts_rebuild)(cpu_mips_t *cpu);
496:
1.1.1.7 ! root 497: void (*mts_shutdown)(cpu_mips_t *cpu);
! 498:
! 499: /* Show MTS statistics */
! 500: void (*mts_show_stats)(cpu_mips_t *cpu);
1.1.1.4 root 501:
1.1.1.7 ! root 502: /* MTS chunk list */
! 503: void *mts_chunk_list;
! 504: void *mts_chunk_free_list;
! 505: void *mts_entry_free_list;
! 506:
! 507: /* MTS cache statistics */
! 508: m_uint64_t mts_misses,mts_lookups;
1.1.1.4 root 509:
510: /* Reverse map for MTS64 */
1.1.1.7 ! root 511: void *mts_rmap[MIPS64_TLB_MAX_ENTRIES];
1.1.1.4 root 512:
513: /* JIT flush method */
514: u_int jit_flush_method;
515:
516: /* Number of compiled pages */
517: u_int compiled_pages;
518:
519: /* Fast memory operations use */
520: u_int fast_memop;
521:
1.1.1.7 ! root 522: /* Address mode (32 or 64 bits) */
! 523: u_int addr_mode;
! 524:
1.1.1.4 root 525: /* Current exec page (non-JIT) info */
526: m_uint64_t njm_exec_page;
527: mips_insn_t *njm_exec_ptr;
528:
529: /* Performance counter (number of instructions executed by CPU) */
530: m_uint64_t perf_counter;
1.1 root 531:
532: /* Memory access log for fault debugging */
533: u_int memlog_pos;
534: memlog_access_t memlog_array[MEMLOG_COUNT];
535:
536: /* Breakpoints */
537: m_uint64_t breakpoints[MIPS64_MAX_BREAKPOINTS];
1.1.1.3 root 538: u_int breakpoints_enabled;
1.1 root 539:
1.1.1.6 root 540: /* Idle PC proposal */
541: struct mips64_idle_pc idle_pc_prop[MIPS64_IDLE_PC_MAX_RES];
542: u_int idle_pc_prop_count;
543:
1.1.1.4 root 544: /* Symtrace */
545: int sym_trace;
546: rbtree_tree *sym_tree;
1.1.1.2 root 547:
1.1.1.4 root 548: /* Next CPU in group */
549: cpu_mips_t *next;
1.1 root 550: };
551:
1.1.1.4 root 552: #define MIPS64_IRQ_LOCK(cpu) pthread_mutex_lock(&(cpu)->irq_lock)
553: #define MIPS64_IRQ_UNLOCK(cpu) pthread_mutex_unlock(&(cpu)->irq_lock)
554:
1.1 root 555: /* Register names */
556: extern char *mips64_gpr_reg_names[];
557:
1.1.1.4 root 558: /* Get cacheability info */
559: int mips64_cca_cached(m_uint8_t val);
560:
561: /* Reset a MIPS64 CPU */
562: int mips64_reset(cpu_mips_t *cpu);
563:
1.1 root 564: /* Initialize a MIPS64 processor */
1.1.1.4 root 565: int mips64_init(cpu_mips_t *cpu);
566:
567: /* Delete a MIPS64 processor */
568: void mips64_delete(cpu_mips_t *cpu);
569:
570: /* Set the CPU PRID register */
571: void mips64_set_prid(cpu_mips_t *cpu,m_uint32_t prid);
572:
573: /* Virtual idle loop */
574: void mips64_idle_loop(cpu_mips_t *cpu);
575:
576: /* Break idle wait state */
577: void mips64_idle_break_wait(cpu_mips_t *cpu);
578:
579: /* Timer IRQ */
580: void *mips64_timer_irq_run(cpu_mips_t *cpu);
581:
582: /* Determine an "idling" PC */
583: int mips64_get_idling_pc(cpu_mips_t *cpu);
1.1 root 584:
585: /* Update the IRQ flag */
586: void mips64_update_irq_flag(cpu_mips_t *cpu);
587:
588: /* Generate an exception */
589: void mips64_trigger_exception(cpu_mips_t *cpu,u_int exc_code,int bd_slot);
590:
591: /*
592: * Increment count register and trigger the timer IRQ if value in compare
593: * register is the same.
594: */
595: fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu);
596:
597: /* Trigger the Timer IRQ */
598: fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu);
599:
600: /* Execute ERET instruction */
601: fastcall void mips64_exec_eret(cpu_mips_t *cpu);
602:
603: /* Execute SYSCALL instruction */
604: fastcall void mips64_exec_syscall(cpu_mips_t *cpu);
605:
606: /* Execute BREAK instruction */
607: fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code);
608:
609: /* Trigger a Trap Exception */
1.1.1.4 root 610: fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu);
1.1 root 611:
612: /* Trigger IRQs */
613: fastcall void mips64_trigger_irq(cpu_mips_t *cpu);
614:
615: /* Set an IRQ */
1.1.1.4 root 616: void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq);
1.1 root 617:
618: /* Clear an IRQ */
1.1.1.4 root 619: void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq);
1.1 root 620:
621: /* DMFC1 */
622: fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
623:
624: /* DMTC1 */
625: fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
626:
627: /* MFC1 */
628: fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
629:
630: /* MTC1 */
631: fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
632:
633: /* Virtual breakpoint */
634: fastcall void mips64_run_breakpoint(cpu_mips_t *cpu);
635:
1.1.1.5 root 636: /* Add a virtual breakpoint */
637: int mips64_add_breakpoint(cpu_mips_t *cpu,m_uint64_t pc);
638:
639: /* Remove a virtual breakpoint */
640: void mips64_remove_breakpoint(cpu_mips_t *cpu,m_uint64_t pc);
641:
1.1.1.4 root 642: /* Debugging for register-jump to address 0 */
643: fastcall void mips64_debug_jr0(cpu_mips_t *cpu);
644:
1.1 root 645: /* Dump registers of a MIPS64 processor */
646: void mips64_dump_regs(cpu_mips_t *cpu);
647:
648: /* Dump a memory block */
649: void mips64_dump_memory(cpu_mips_t *cpu,m_uint64_t vaddr,u_int count);
650:
651: /* Dump the stack */
652: void mips64_dump_stack(cpu_mips_t *cpu,u_int count);
653:
654: /* Save the CPU state into a file */
655: int mips64_save_state(cpu_mips_t *cpu,char *filename);
656:
1.1.1.4 root 657: /* Load a raw image into the simulated memory */
658: int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr);
659:
660: /* Load an ELF image into the simulated memory */
1.1.1.7 ! root 661: int mips64_load_elf_image(cpu_mips_t *cpu,char *filename,int skip_load,
1.1.1.4 root 662: m_uint32_t *entry_point);
663:
664: /* Symbol lookup */
665: struct symbol *mips64_sym_lookup(cpu_mips_t *cpu,m_uint64_t addr);
666:
667: /* Insert a new symbol */
668: struct symbol *mips64_sym_insert(cpu_mips_t *cpu,char *name,m_uint64_t addr);
669:
670: /* Create the symbol tree */
671: int mips64_sym_create_tree(cpu_mips_t *cpu);
672:
673: /* Load a symbol file */
674: int mips64_sym_load_file(cpu_mips_t *cpu,char *filename);
675:
1.1 root 676: #endif
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