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1.1 root 1: /*
2: * Cisco router simulation platform.
3: * Copyright (c) 2005,2006 Christophe Fillot ([email protected])
4: *
5: * MIPS64 JIT compiler.
6: */
7:
8: #ifndef __MIPS64_JIT_H__
9: #define __MIPS64_JIT_H__
10:
11: #include "utils.h"
1.1.1.2 ! root 12: #include "sbox.h"
1.1 root 13:
14: /* Size of executable page area (in Mb) */
15: #ifndef __CYGWIN__
16: #define MIPS_EXEC_AREA_SIZE 64
17: #else
18: #define MIPS_EXEC_AREA_SIZE 16
19: #endif
20:
21: /* Buffer size for JIT code generation */
22: #define MIPS_JIT_BUFSIZE 32768
23:
24: /* Maximum number of X86 chunks */
25: #define MIPS_JIT_MAX_CHUNKS 32
26:
1.1.1.2 ! root 27: /* Size of hash for PC lookup */
! 28: #define MIPS_JIT_PC_HASH_BITS 16
! 29: #define MIPS_JIT_PC_HASH_MASK ((1 << MIPS_JIT_PC_HASH_BITS) - 1)
! 30: #define MIPS_JIT_PC_HASH_SIZE (1 << MIPS_JIT_PC_HASH_BITS)
! 31:
1.1 root 32: /* Instruction jump patch */
33: struct mips64_insn_patch {
34: u_char *jit_insn;
35: m_uint64_t mips_pc;
36: };
37:
38: /* Instruction patch table */
39: #define MIPS64_INSN_PATCH_TABLE_SIZE 32
40:
41: struct mips64_jit_patch_table {
42: struct mips64_insn_patch patches[MIPS64_INSN_PATCH_TABLE_SIZE];
43: u_int cur_patch;
44: struct mips64_jit_patch_table *next;
45: };
46:
47: /* MIPS64 translated code block */
48: struct mips64_jit_tcb {
49: m_uint64_t start_pc;
50: u_char **jit_insn_ptr;
51: m_uint64_t acc_count;
52: mips_insn_t *mips_code;
53: u_int mips_trans_pos;
54: u_int jit_chunk_pos;
55: u_char *jit_ptr;
56: insn_exec_page_t *jit_buffer;
57: insn_exec_page_t *jit_chunks[MIPS_JIT_MAX_CHUNKS];
58: struct mips64_jit_patch_table *patch_table;
59: mips64_jit_tcb_t *prev,*next;
60: #if DEBUG_BLOCK_TIMESTAMP
61: m_uint64_t tm_first_use,tm_last_use;
62: #endif
63: };
64:
65: /* MIPS instruction recognition */
66: struct mips64_insn_tag {
67: int (*emit)(cpu_mips_t *cpu,mips64_jit_tcb_t *,mips_insn_t);
68: m_uint32_t mask,value;
69: int delay_slot;
70: };
71:
72: /* MIPS jump instruction (for block scan) */
73: struct mips64_insn_jump {
74: char *name;
75: m_uint32_t mask,value;
76: int offset_bits;
77: int relative;
78: };
79:
80: /* Get the JIT instruction pointer in a translated block */
81: static forced_inline
82: u_char *mips64_jit_tcb_get_host_ptr(mips64_jit_tcb_t *b,m_uint64_t vaddr)
83: {
1.1.1.2 ! root 84: m_uint32_t offset;
1.1 root 85:
1.1.1.2 ! root 86: offset = ((m_uint32_t)vaddr & MIPS_MIN_PAGE_IMASK) >> 2;
1.1 root 87: return(b->jit_insn_ptr[offset]);
88: }
89:
1.1.1.2 ! root 90: /* Check if the specified address belongs to the specified block */
! 91: static forced_inline
! 92: int mips64_jit_tcb_local_addr(mips64_jit_tcb_t *block,m_uint64_t vaddr,
! 93: u_char **jit_addr)
! 94: {
! 95: if ((vaddr & MIPS_MIN_PAGE_MASK) == block->start_pc) {
! 96: *jit_addr = mips64_jit_tcb_get_host_ptr(block,vaddr);
! 97: return(1);
! 98: }
! 99:
! 100: return(0);
! 101: }
! 102:
! 103: /* Check if PC register matches the compiled block virtual address */
! 104: static forced_inline
! 105: int mips64_jit_tcb_match(cpu_mips_t *cpu,mips64_jit_tcb_t *block)
! 106: {
! 107: m_uint64_t vpage;
! 108:
! 109: vpage = cpu->pc & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK;
! 110: return(block->start_pc == vpage);
! 111: }
! 112:
! 113: /* Compute the hash index for the specified PC value */
! 114: static forced_inline m_uint32_t mips64_jit_get_pc_hash(m_uint64_t pc)
! 115: {
! 116: m_uint32_t page_hash;
! 117:
! 118: page_hash = sbox_u32(pc >> MIPS_MIN_PAGE_SHIFT);
! 119: return((page_hash ^ (page_hash >> 12)) & MIPS_JIT_PC_HASH_MASK);
! 120: }
! 121:
1.1 root 122: /* Check if there are pending IRQ */
123: extern void mips64_check_pending_irq(mips64_jit_tcb_t *b);
124:
125: /* Initialize instruction lookup table */
126: void mips64_jit_create_ilt(void);
127:
128: /* Initialize the JIT structure */
129: int mips64_jit_init(cpu_mips_t *cpu);
130:
131: /* Flush the JIT */
132: u_int mips64_jit_flush(cpu_mips_t *cpu,u_int threshold);
133:
134: /* Shutdown the JIT */
135: void mips64_jit_shutdown(cpu_mips_t *cpu);
136:
1.1.1.2 ! root 137: /* Check if an instruction is in a delay slot or not */
! 138: int mips64_jit_is_delay_slot(mips64_jit_tcb_t *b,m_uint64_t pc);
! 139:
1.1 root 140: /* Fetch a MIPS instruction and emit corresponding x86 translated code */
141: struct mips64_insn_tag *mips64_jit_fetch_and_emit(cpu_mips_t *cpu,
142: mips64_jit_tcb_t *block,
143: int delay_slot);
144:
145: /* Record a patch to apply in a compiled block */
146: int mips64_jit_tcb_record_patch(mips64_jit_tcb_t *block,u_char *x86_ptr,
147: m_uint64_t vaddr);
148:
149: /* Free an instruction block */
150: void mips64_jit_tcb_free(cpu_mips_t *cpu,mips64_jit_tcb_t *block,
151: int list_removal);
152:
153: /* Execute compiled MIPS code */
154: void *mips64_jit_run_cpu(cpu_gen_t *cpu);
155:
156: /* Set the Pointer Counter (PC) register */
157: void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc);
158:
159: /* Set the Return Address (RA) register */
160: void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc);
161:
162: /* Single-step operation */
163: void mips64_emit_single_step(mips64_jit_tcb_t *b,mips_insn_t insn);
164:
165: /* Virtual Breakpoint */
166: void mips64_emit_breakpoint(mips64_jit_tcb_t *b);
167:
168: /* Emit unhandled instruction code */
169: int mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b);
170:
171: /*
172: * Increment count register and trigger the timer IRQ if value in compare
173: * register is the same.
174: */
175: void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b);
176:
177: /* Increment the number of executed instructions (performance debugging) */
178: void mips64_inc_perf_counter(mips64_jit_tcb_t *b);
179:
180: #endif
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