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1.1 root 1: /* $NetBSD: pcireg.h,v 1.19 1998/12/21 20:31:54 drochner Exp $ */
2:
3: /*
4: * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
5: * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Charles M. Hannum.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31: */
32:
33: #ifndef _DEV_PCI_PCIREG_H_
34: #define _DEV_PCI_PCIREG_H_
35:
36: /*
37: * Standardized PCI configuration information
38: *
39: * XXX This is not complete.
40: */
41:
42: /*
43: * Device identification register; contains a vendor ID and a device ID.
44: */
45: #define PCI_ID_REG 0x00
46:
47: typedef u_int16_t pci_vendor_id_t;
48: typedef u_int16_t pci_product_id_t;
49:
50: #define PCI_VENDOR_SHIFT 0
51: #define PCI_VENDOR_MASK 0xffff
52: #define PCI_VENDOR(id) \
53: (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
54:
55: #define PCI_PRODUCT_SHIFT 16
56: #define PCI_PRODUCT_MASK 0xffff
57: #define PCI_PRODUCT(id) \
58: (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
59:
60: /*
61: * Command and status register.
62: */
63: #define PCI_COMMAND_STATUS_REG 0x04
64:
65: #define PCI_COMMAND_IO_ENABLE 0x00000001
66: #define PCI_COMMAND_MEM_ENABLE 0x00000002
67: #define PCI_COMMAND_MASTER_ENABLE 0x00000004
68: #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
69: #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
70: #define PCI_COMMAND_PALETTE_ENABLE 0x00000020
71: #define PCI_COMMAND_PARITY_ENABLE 0x00000040
72: #define PCI_COMMAND_STEPPING_ENABLE 0x00000080
73: #define PCI_COMMAND_SERR_ENABLE 0x00000100
74: #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
75:
76: #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
77: #define PCI_STATUS_66MHZ_SUPPORT 0x00200000
78: #define PCI_STATUS_UDF_SUPPORT 0x00400000
79: #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
80: #define PCI_STATUS_PARITY_ERROR 0x01000000
81: #define PCI_STATUS_DEVSEL_FAST 0x00000000
82: #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
83: #define PCI_STATUS_DEVSEL_SLOW 0x04000000
84: #define PCI_STATUS_DEVSEL_MASK 0x06000000
85: #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
86: #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
87: #define PCI_STATUS_MASTER_ABORT 0x20000000
88: #define PCI_STATUS_SPECIAL_ERROR 0x40000000
89: #define PCI_STATUS_PARITY_DETECT 0x80000000
90:
91: /*
92: * PCI Class and Revision Register; defines type and revision of device.
93: */
94: #define PCI_CLASS_REG 0x08
95:
96: typedef u_int8_t pci_class_t;
97: typedef u_int8_t pci_subclass_t;
98: typedef u_int8_t pci_interface_t;
99: typedef u_int8_t pci_revision_t;
100:
101: #define PCI_CLASS_SHIFT 24
102: #define PCI_CLASS_MASK 0xff
103: #define PCI_CLASS(cr) \
104: (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
105:
106: #define PCI_SUBCLASS_SHIFT 16
107: #define PCI_SUBCLASS_MASK 0xff
108: #define PCI_SUBCLASS(cr) \
109: (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
110:
111: #define PCI_INTERFACE_SHIFT 8
112: #define PCI_INTERFACE_MASK 0xff
113: #define PCI_INTERFACE(cr) \
114: (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
115:
116: #define PCI_REVISION_SHIFT 0
117: #define PCI_REVISION_MASK 0xff
118: #define PCI_REVISION(cr) \
119: (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
120:
121: /* base classes */
122: #define PCI_CLASS_PREHISTORIC 0x00
123: #define PCI_CLASS_MASS_STORAGE 0x01
124: #define PCI_CLASS_NETWORK 0x02
125: #define PCI_CLASS_DISPLAY 0x03
126: #define PCI_CLASS_MULTIMEDIA 0x04
127: #define PCI_CLASS_MEMORY 0x05
128: #define PCI_CLASS_BRIDGE 0x06
129: #define PCI_CLASS_COMMUNICATIONS 0x07
130: #define PCI_CLASS_SYSTEM 0x08
131: #define PCI_CLASS_INPUT 0x09
132: #define PCI_CLASS_DOCK 0x0a
133: #define PCI_CLASS_PROCESSOR 0x0b
134: #define PCI_CLASS_SERIALBUS 0x0c
135: #define PCI_CLASS_UNDEFINED 0xff
136:
137: /* 0x00 prehistoric subclasses */
138: #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
139: #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
140:
141: /* 0x01 mass storage subclasses */
142: #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
143: #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
144: #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
145: #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
146: #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
147: #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
148:
149: /* 0x02 network subclasses */
150: #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
151: #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
152: #define PCI_SUBCLASS_NETWORK_FDDI 0x02
153: #define PCI_SUBCLASS_NETWORK_ATM 0x03
154: #define PCI_SUBCLASS_NETWORK_MISC 0x80
155:
156: /* 0x03 display subclasses */
157: #define PCI_SUBCLASS_DISPLAY_VGA 0x00
158: #define PCI_SUBCLASS_DISPLAY_XGA 0x01
159: #define PCI_SUBCLASS_DISPLAY_MISC 0x80
160:
161: /* 0x04 multimedia subclasses */
162: #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
163: #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
164: #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
165:
166: /* 0x05 memory subclasses */
167: #define PCI_SUBCLASS_MEMORY_RAM 0x00
168: #define PCI_SUBCLASS_MEMORY_FLASH 0x01
169: #define PCI_SUBCLASS_MEMORY_MISC 0x80
170:
171: /* 0x06 bridge subclasses */
172: #define PCI_SUBCLASS_BRIDGE_HOST 0x00
173: #define PCI_SUBCLASS_BRIDGE_ISA 0x01
174: #define PCI_SUBCLASS_BRIDGE_EISA 0x02
175: #define PCI_SUBCLASS_BRIDGE_MC 0x03
176: #define PCI_SUBCLASS_BRIDGE_PCI 0x04
177: #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
178: #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
179: #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
180: #define PCI_SUBCLASS_BRIDGE_MISC 0x80
181:
182: /* 0x07 communications subclasses */
183: #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
184: #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
185: #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
186:
187: /* 0x08 system subclasses */
188: #define PCI_SUBCLASS_SYSTEM_PIC 0x00
189: #define PCI_SUBCLASS_SYSTEM_DMA 0x01
190: #define PCI_SUBCLASS_SYSTEM_TIMER 0x02
191: #define PCI_SUBCLASS_SYSTEM_RTC 0x03
192: #define PCI_SUBCLASS_SYSTEM_MISC 0x80
193:
194: /* 0x09 input subclasses */
195: #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
196: #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
197: #define PCI_SUBCLASS_INPUT_MOUSE 0x02
198: #define PCI_SUBCLASS_INPUT_MISC 0x80
199:
200: /* 0x0a dock subclasses */
201: #define PCI_SUBCLASS_DOCK_GENERIC 0x00
202: #define PCI_SUBCLASS_DOCK_MISC 0x80
203:
204: /* 0x0b processor subclasses */
205: #define PCI_SUBCLASS_PROCESSOR_386 0x00
206: #define PCI_SUBCLASS_PROCESSOR_486 0x01
207: #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
208: #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
209: #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
210: #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
211:
212: /* 0x0c serial bus subclasses */
213: #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
214: #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
215: #define PCI_SUBCLASS_SERIALBUS_SSA 0x02
216: #define PCI_SUBCLASS_SERIALBUS_USB 0x03
217: #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04
218:
219: /*
220: * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
221: */
222: #define PCI_BHLC_REG 0x0c
223:
224: #define PCI_BIST_SHIFT 24
225: #define PCI_BIST_MASK 0xff
226: #define PCI_BIST(bhlcr) \
227: (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
228:
229: #define PCI_HDRTYPE_SHIFT 16
230: #define PCI_HDRTYPE_MASK 0xff
231: #define PCI_HDRTYPE(bhlcr) \
232: (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
233:
234: #define PCI_HDRTYPE_TYPE(bhlcr) \
235: (PCI_HDRTYPE(bhlcr) & 0x7f)
236: #define PCI_HDRTYPE_MULTIFN(bhlcr) \
237: ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
238:
239: #define PCI_LATTIMER_SHIFT 8
240: #define PCI_LATTIMER_MASK 0xff
241: #define PCI_LATTIMER(bhlcr) \
242: (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
243:
244: #define PCI_CACHELINE_SHIFT 0
245: #define PCI_CACHELINE_MASK 0xff
246: #define PCI_CACHELINE(bhlcr) \
247: (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
248:
249: /*
250: * Mapping registers
251: */
252: #define PCI_MAPREG_START 0x10
253: #define PCI_MAPREG_END 0x28
254:
255: #define PCI_MAPREG_TYPE(mr) \
256: ((mr) & PCI_MAPREG_TYPE_MASK)
257: #define PCI_MAPREG_TYPE_MASK 0x00000001
258:
259: #define PCI_MAPREG_TYPE_MEM 0x00000000
260: #define PCI_MAPREG_TYPE_IO 0x00000001
261:
262: #define PCI_MAPREG_MEM_TYPE(mr) \
263: ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
264: #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
265:
266: #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
267: #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
268: #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
269:
270: #define PCI_MAPREG_MEM_CACHEABLE(mr) \
271: (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0)
272: #define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008
273:
274: #define PCI_MAPREG_MEM_ADDR(mr) \
275: ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
276: #define PCI_MAPREG_MEM_SIZE(mr) \
277: (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
278: #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
279:
280: #define PCI_MAPREG_IO_ADDR(mr) \
281: ((mr) & PCI_MAPREG_IO_ADDR_MASK)
282: #define PCI_MAPREG_IO_SIZE(mr) \
283: (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
284: #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
285:
286: /*
287: * Cardbus CIS pointer (PCI rev. 2.1)
288: */
289: #define PCI_CARDBUS_CIS_REG 0x28
290:
291: /*
292: * Subsystem identification register; contains a vendor ID and a device ID.
293: * Types/macros for PCI_ID_REG apply.
294: * (PCI rev. 2.1)
295: */
296: #define PCI_SUBSYS_ID_REG 0x2c
297:
298: /*
299: * capabilities link list (PCI rev. 2.2)
300: */
301: #define PCI_CAPLISTPTR_REG 0x34
302: #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
303: #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
304: #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
305: #define PCI_CAP_PWRMGMT 1
306: #define PCI_CAP_AGP 2
307: #define PCI_CAP_VPD 3
308: #define PCI_CAP_SLOTID 4
309: #define PCI_CAP_MBI 5
310: #define PCI_CAP_HOTSWAP 6
311:
312: /*
313: * Interrupt Configuration Register; contains interrupt pin and line.
314: */
315: #define PCI_INTERRUPT_REG 0x3c
316:
317: typedef u_int8_t pci_intr_pin_t;
318: typedef u_int8_t pci_intr_line_t;
319:
320: #define PCI_INTERRUPT_PIN_SHIFT 8
321: #define PCI_INTERRUPT_PIN_MASK 0xff
322: #define PCI_INTERRUPT_PIN(icr) \
323: (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
324:
325: #define PCI_INTERRUPT_LINE_SHIFT 0
326: #define PCI_INTERRUPT_LINE_MASK 0xff
327: #define PCI_INTERRUPT_LINE(icr) \
328: (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
329:
330: #define PCI_INTERRUPT_PIN_NONE 0x00
331: #define PCI_INTERRUPT_PIN_A 0x01
332: #define PCI_INTERRUPT_PIN_B 0x02
333: #define PCI_INTERRUPT_PIN_C 0x03
334: #define PCI_INTERRUPT_PIN_D 0x04
335:
336: #endif /* _DEV_PCI_PCIREG_H_ */
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