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1.1 root 1: #ifndef AHA154X_H
2: #define AHA154X_H
3:
4: /*
5: * describe the data structures neccessary to
6: * access the Hard/Firmware of the AHA-154x family.
7: *
8: * First the hardware which consists of three I/O ports.
9: */
10:
11: #define AHA_CONTROL (0*0+0)
12: #define AHA_HARDRESET 0x80 /* Hard */
13: #define AHA_SOFTRESET 0x40 /* Soft */
14: #define AHA_INTRRESET 0x20 /* Interrupt */
15: #define AHA_SCSIRESET 0x10 /* SCSI */
16: /* ... Reserved ... */
17:
18: #define AHA_STATUS (0*0+0)
19: #define AHA_SELFTEST 0x80 /* SELF TEST in progress */
20: #define AHA_DIAGFAIL 0x40 /* DIAGnostics FAILed */
21: #define AHA_INITMAIL 0x20 /* INIT of MAILbox required */
22: #define AHA_SCSIIDLE 0x10 /* SCSI host adaptor IDLE */
23: #define AHA_CDOPFULL 0x08 /* Command/Data Out Port FULL */
24: #define AHA_DIPFULL 0x04 /* Data In Port FULL */
25: /* ... Reserved ... */
26: #define AHA_INVDCMD 0x01 /* INValiD CoMmanD */
27:
28: #define AHA_READ (0*0+1)
29: #define AHA_WRITE (0*0+1)
30:
31: #define AHA_INTERRUPT (0*0+2)
32: #define AHA_ANY_INTER 0x80
33: /* ... Reserved ... */
34: #define AHA_RESETED 0x08
35: #define AHA_CMD_DONE 0x04
36: #define AHA_MBO_EMPTY 0x02
37: #define AHA_MBI_STORED 0x01
38: #define AHA_ALL_INTERRUPTS \
39: (AHA_RESETED|AHA_CMD_DONE|AHA_MBO_EMPTY|AHA_MBI_STORED)
40:
41: /*
42: * Command Control Block Opcodes.
43: */
44: #define AHA_OP_SIC 0x00 /* SCSI Initiator Command Control Block */
45: #define AHA_OP_TCC 0x01 /* SCSI Target Command Control Block */
46: #define AHA_OP_SIC_SG 0x02 /* SCSI Initiator Command Control Block
47: * with Scatter/Gather */
48: #define AHA_OP_SIC_res 0x03 /* SCSI Initiator Command,
49: * residual data length returned. */
50: #define AHA_OP_SIC_SG_res 0x04 /* SCSI Initiator Command
51: * with Scatter/Gather,
52: * residual data length returned. */
53: #define AHA_OP_SPQR 0x81 /* SCSI Bus Device Reset
54: * (a work of the people :-) */
55: #define AHA_OP_INVALID 0x22 /* This randomly chosen command is used to
56: * mark a ccb as invalidated. */
57:
58: /*
59: * Adapter Firmware Components
60: */
61: #define AHA_DO_NOP 0x00
62: #define AHA_DO_MAILBOX_INIT 0x01
63: /* DATA send = MB count, MB adr[3] */
64: #define AHA_DO_SCSI_START 0x02
65: #define AHA_DO_BIOS_START 0x03
66: #define AHA_DO_INQUIRY 0x04
67: /* DATA recv = board id (ASCII)
68: special options id (standard = 'A')
69: HW rev level (ASCII)
70: FirmWare rev level (ASCII)*/
71: #define AHA_DO_MBO_INTR_ON 0x05
72: /* DATA send = 0/1 = Dis/Enable INTR */
73: #define AHA_DO_SET_TIMEOUT 0x06
74: /* DATA send = 0/1 = Dis/Enable Timeout
75: ...reserved...
76: value[MSB] default = 250 millisec
77: value[LSB] */
78: #define AHA_DO_BUS_ON_TIME 0x07
79: /* DATA send = 2 to 15 microsec. */
80: #define AHA_DO_BUS_OFF_TIME 0x08
81: /* DATA send = 1 to 64 microsec. */
82: #define AHA_DO_XFER_SPEED 0x09
83: #define AHA_SPEED_5_0_MB 0x00
84: #define AHA_SPEED_6_7_MB 0x01
85: #define AHA_SPEED_8_0_MB 0x02
86: #define AHA_SPEED_10_MB 0x03
87: #define AHA_SPEED_5_7_MB 0x04
88: #define AHA_SPEED_CUSTOM 0x80
89: /* see Chap. 5.1.1.10 */
90: #define AHA_DO_GET_DEVICES 0x0A
91: /* DATA recv = eight bytes, one per target
92: whereby each bit indicates if a LUN is installed */
93: #define AHA_DO_GET_CONFIG 0x0B
94: /* DATA recv = DMA Arb. Priority,
95: Inter. Channel,
96: SCSI Id. */
97: #define AHA_DO_TARGET_ON 0x0C
98: /* DATA send = 0/1 = Dis/Enable Target Mode
99: LUN mask, 1 -> LUN will respond in Target Mode */
100: #define AHA_DO_GET_SETUP 0x0D
101: /* DATA send = n, count requested, 0 -> 256 bytes
102: DATA recv = 00 SDT + Parity,
103: 01 Transfer Speed,
104: 02 Bus On Time,
105: 03 Bus Off Time,
106: 04 # MB's,
107: 05-07 MailBox Adr,
108: 08-0F Sync Transfer Agreements,
109: 10-FF Reserved (default 00) */
110:
111: /* ... reserved ... */
112: #define AHA_DO_PUT_CH2_BUF 0x1A
113: /* DATA send = 00-02 Buffer Area (64 bytes) Address */
114: #define AHA_DO_GET_CH2_BUF 0x1B
115: /* DATA send = 00-02 Buffer Area (64 bytes) Address */
116: #define AHA_DO_PUT_FIFO_BUF 0x1C
117: /* DATA send = 00-02 FIFO Area (54 bytes) Address */
118: #define AHA_DO_GET_FIFO_BUF 0x1D
119: /* DATA send = 00-02 FIFO Area (54 bytes) Address */
120: /* ... reserved ... */
121: #define AHA_DO_ECHO_CMD_DATA 0x1F
122: /* DATA send = 1 byte
123: DATA recv = 1 byte, hopefully the same one ! */
124:
125: /* A P3 is a 3 byte physical address. */
126: typedef unsigned char P3[3];
127:
128: typedef struct {
129: # define MBO_IS_FREE 0x00
130: # define MBO_TO_START 0x01
131: # define MBO_IS_ABORT 0x02
132: char state;
133: P3 ccb_adr;
134: } MBO;
135:
136: /*
137: * MBI for CCB completed
138: */
139: typedef struct {
140: # define MBI_IS_FREE 0x00
141: # define MBI_NO_ERROR 0x01
142: # define MBI_IS_ABORT 0x02
143: # define MBI_NOT_FOUND 0x03
144: # define MBI_HAS_ERROR 0x04
145: char state;
146: /* MBI for CCB required */
147: /* byte 0 */
148: # define MBI_CCB_REQUEST 0x10
149: /* byte 1 */
150: # define MBI_MSK_INITOR 0xE0
151: # define MBI_WAS_READ 0x10
152: # define MBI_WAS_WRITE 0x08
153: # define MBI_MSK_LUN 0x03
154: /* byte 2,3 are data len */
155: P3 ccb_adr;
156: } MBI;
157:
158: #ifndef MAX_SCSICMD
159: #define MAX_SCSICMD 14
160: #endif /* MAX_SCSICMD */
161:
162: #ifndef MAX_SENSEDATA
163: #define MAX_SENSEDATA 27
164: #endif /* MAX_SENSEDATA */
165:
166: typedef struct {
167: unsigned char cmd;
168: P3 adr;
169: } mailentry;
170:
171: #define SENSE_UNIT_ATTENTION 6
172: #define CHECK_TARGET_STATUS 2
173: typedef struct {
174: char opcode;
175: char target;
176: #define AHA_CCB_DATA_OUT 0x10
177: #define AHA_CCB_DATA_IN 0x08
178: char cmdlen;
179: char senselen;
180: P3 datalen;
181: P3 dataptr;
182: P3 linkptr;
183: char linkid;
184: char hoststatus;
185: char targetstatus;
186: char reserve[2];
187: unsigned char cmd_status[MAX_SCSICMD+MAX_SENSEDATA];
188: scsi_work_t *ccb_sw;
189: unsigned char buffer[1];
190: } ccb_t;
191:
192: #ifdef _I386
193: /* These macros are for stashing away P3 addresses for ccbs. */
194: #define ccb_forget( a_ccb ) mem_forget( a_ccb )
195: #define ccb_remember( a_ccb, a_p3 ) \
196: mem_remember( (a_ccb), aha_p3_to_l( a_p3 ) )
197: #define ccb_recall( a_p3 ) mem_recall( aha_p3_to_l( a_p3 ) )
198:
199: typedef struct {
200: P3 size;
201: P3 addr;
202: } DSL_ENTRY;
203: #endif /* _I386 */
204:
205: #endif /* of AHA154X_H */
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