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1.1 root 1: /* (-lgl
2: * COHERENT Driver Kit Version 1.1.0
3: * Copyright (c) 1982, 1990 by Mark Williams Company.
4: * All rights reserved. May not be copied without permission.
5: *
6: * $Log: ins8250.h,v $
7: * Revision 1.2 92/09/29 09:26:40 bin
8: * updated with kernel 63 src
9: *
10: * Revision 1.2 91/12/10 07:59:06 hal
11: * Add FIFO registers and constants.
12: * Add uart type constants.
13: *
14: * Revision 1.1 91/11/16 16:31:59 hal
15: * Used thru COHERENT 3.2.0.
16: *
17: -lgl) */
18: /*
19: * INS 8250 ACIA Register Definitions
20: */
21: #ifndef INS8250_H
22: #define INS8250_H
23:
24: /*
25: * Register Offsets
26: */
27:
28: #define DREG 0 /* Data Register (DLAB=0) */
29: #define IER 1 /* Interrupt Enable Register (DLAB=0) */
30: #define IIR 2 /* Interrupt Identification Register */
31: #define FCR 2 /* FIFO Control Register */
32: #define LCR 3 /* Line Control Register */
33: #define MCR 4 /* Modem Control Register */
34: #define LSR 5 /* Line Status Register */
35: #define MSR 6 /* Modem Status Register */
36: #define SCR 7 /* Scratch Register */
37:
38: #define DLL 0 /* Divisor Latch Low Register (DLAB=1) */
39: #define DLH 1 /* Divisor Latch High Register (DLAB=1) */
40:
41: /*
42: * Interrupt Enable Register (IER) - bits 4-7 zeroed
43: */
44:
45: #define IE_RxI 0x01 /* Enable Received Data Available Intr. */
46: #define IE_TxI 0x02 /* Enable Transmit Buf Empty Interrupt */
47: #define IE_LSI 0x04 /* Enable Line Status Interrupt */
48: #define IE_MSI 0x08 /* Enable Modem Status Interrupt */
49:
50: #define IENABLE (IE_RxI | IE_TxI | IE_LSI | IE_MSI)
51:
52:
53: /*
54: * Interrupt Identification Register (IIR)
55: */
56:
57: #define Rt_INTR 0x0C /* Received Char Timeout Interrupt */
58: #define LS_INTR 0x06 /* Receiver Line Status Interrupt */
59: #define Rx_INTR 0x04 /* Received Data Available Interrupt */
60: #define Tx_INTR 0x02 /* Transmit Buf Empty Interrupt */
61: #define MS_INTR 0x00 /* Modem Status Interrupt */
62:
63:
64: /*
65: * FIFO Control Register (FCR)
66: */
67:
68: #define FC_ENABLE 0x01 /* Enable on-chip FIFO (16550A only) */
69: #define FC_Rx_RST 0x02 /* Reset RCVR FIFO */
70: #define FC_Tx_RST 0x04 /* Reset XMIT FIFO */
71: #define FC_Rx_01 0x00 /* Rx Irpt on 1 char in rcvr FIFO */
72: #define FC_Rx_04 0x40 /* Rx Irpt on 4 char in rcvr FIFO */
73: #define FC_Rx_08 0x80 /* Rx Irpt on 8 char in rcvr FIFO */
74: #define FC_Rx_14 0xC0 /* Rx Irpt on 14 char in rcvr FIFO */
75:
76: /*
77: * Line Control Register (LCR)
78: */
79:
80: #define LC_CSIZE 0x03 /* Character Size: */
81: #define LC_CS5 0 /* 5 bits */
82: #define LC_CS6 0x01 /* 6 bits */
83: #define LC_CS7 0x02 /* 7 bits */
84: #define LC_CS8 0x03 /* 8 bits */
85:
86: #define LC_STOPB 0x04 /* 1 1/2 (CS5) or 2 (CS6-CS8) stop bits */
87: #define LC_PARENB 0x08 /* Parity Enable */
88:
89: #define LC_PARITY 0x30 /* Parity Selection: */
90: #define LC_PARODD 0 /* Odd Parity */
91: #define LC_PAREVEN 0x10 /* Even Parity */
92: #define LC_PARLO 0x20 /* Low Stick */
93: #define LC_PARHI 0x30 /* High Stick */
94: #define LC_SBRK 0x40 /* Set Break */
95: #define LC_DLAB 0x80 /* Divisor Latch Access Bit (DLAB) */
96:
97: /*
98: * Modem Control Register (MCR) - bits 5..7 zeroed
99: */
100: #define MC_DTR 0x01 /* Data Terminal Ready */
101: #define MC_RTS 0x02 /* Request to Send */
102: #define MC_OUT1 0x04 /* Auxiliary user-designated output 1 */
103: #define MC_OUT2 0x08 /* Auxiliary user-designated output 2 */
104: #define MC_OUTS 0x0C /* Both OUT signals */
105: #define MC_LOOP 0x10 /* Loopback enable (diagnostic feature) */
106:
107: /*
108: * Line Status Register (LSR) - bit 7 zeroed
109: */
110: #define LS_RxRDY 0x01 /* Receiver Data Ready */
111: #define LS_OVER 0x02 /* Overrun Error */
112: #define LS_PARITY 0x04 /* Parity Error */
113: #define LS_FRAME 0x08 /* Framing Error */
114: #define LS_BREAK 0x10 /* Break Interrupt Indicator */
115: #define LS_TxRDY 0x20 /* Transmitter Ready for Data */
116: #define LS_TxIDLE 0x40 /* Transmitter Idle */
117:
118: /*
119: * Modem Status Register (MSR)
120: */
121: #define MS_DCTS 0x01 /* Delta Clear to Send */
122: #define MS_DDSR 0x02 /* Delta Data Set Ready */
123: #define MS_TERI 0x04 /* Trailing Edge of Ring Indicator */
124: #define MS_DRLSD 0x08 /* Delta Rx Line Signal Detect */
125: #define MS_CTS 0x10 /* Clear To Send */
126: #define MS_DSR 0x20 /* Data Set Ready */
127: #define MS_RI 0x40 /* Ring Indicator */
128: #define MS_RLSD 0x80 /* Receive Line Signal Detect */
129:
130: /*
131: * Uart-sense types.
132: */
133: #define US_NONE 0
134: #define US_8250 1
135: #define US_16450 2
136: #define US_16550 3
137: #define US_16550A 4 /* The only one with usable on-chip FIFO */
138: #define US_UNKNOWN -1
139:
140: #endif
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