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1.1 root 1: /* (-lgl
2: * COHERENT Driver Kit Version 2.0
3: * Copyright (c) 1982, 1992 by Mark Williams Company.
4: * All rights reserved. May not be copied without permission.
5: -lgl) */
6: #ifndef MMU_H
7: #define MMU_H
8:
9: #ifdef _I386
10: #ifndef TYPES_H
11: #include <sys/types.h>
12: #endif
13: #ifndef UPROC_H
14: #include <sys/uproc.h>
15: #endif
16:
17: /* A click is a 4K byte paragraph.
18: * a segment is a 4 megabyte paragraph (level 1 page table entry)
19: */
20:
21: #define UII_BASE 0x00400000L /* base for sep I/D l.out text */
22:
23: #define SEG_ILL 0x00 /* The empty page table entry. */
24: #define SEG_PRE 0x01 /* Present bit. */
25: #define SEG_SRO 0x01 /* Read by system only. */
26: #define SEG_SRW 0x03 /* Read/Write by system only. */
27: #define SEG_RO 0x05 /* Read only by anybody. */
28: #define SEG_BITS 0x07 /* Permissions bits for a pte. */
29: #define SEG_RW 0x07 /* Read/Write by anybody. */
30: #define SEG_ACD 0x20 /* Page has been accessed. */
31: #define SEG_UPD 0x40 /* Page has been updated. */
32: /*
33: * SEG_NPL is for pages which are not from the sysmem pool.
34: * This includes pages representing video memory attached to
35: * user data.
36: * The SEG_NPL bit is not a real page table entry flag, and so is
37: * masked out when CPU page tables are loaded from process data.
38: */
39: #define SEG_NPL 0x80 /* Page is not in sysmem pool. */
40:
41: #define DIR_RW 0x07 /* us=us0|us1; rw=rw0&rw1; Intel's sOOO logical*/
42:
43: #define SEG_386_UI 0x08 /* [ 0000 0000 .. FFFF FFFF ] */
44: #define SEG_386_UD 0x10
45: #define SEG_386_KI 0x18
46: #define SEG_386_KD 0x21 /* kernel data in ring 1 */
47: #define SEG_286_UI 0x28
48: #define SEG_286_UD 0x30
49: #define SEG_TSS 0x38
50: #define SEG_ROM 0x40
51: #define SEG_VIDEOa 0x48
52: #define SEG_VIDEOb 0x50
53: #define SEG_386_II 0x58
54: #define SEG_386_ID 0x60
55: #define SEG_286_UII 0x68 /* UI -i */
56: #define SEG_LDT 0x70
57: #define SEG_RNG0_STK 0x78 /* lower limit of 0xFFFFF000 */
58: #define SEG_RNG0_TXT 0x80
59: #define SEG_RNG1_STK 0x88
60:
61: #define SEG_VIRT 0x100 /* pseudo bit for kxcopy */
62:
63: #define R_USR 0x03 /* user privilege level */
64: #define SEG_PL 0x03 /* privilege level mask */
65:
66: #define DPL_0 0x00 /* privilege level 0 */
67: #define DPL_1 0x01 /* privilege level 1 */
68: #define DPL_2 0x02 /* privilege level 2 */
69: #define DPL_3 0x03 /* privilege level 3 */
70:
71: /*
72: * These addresses are all in clicks.
73: */
74: #define ROM 0xFFFC0 /* BIOS virtual address. */
75: #define VIDEOa 0xFFFB0 /* CGA video virtual address. */
76: #define VIDEOb 0xFFFA0 /* Mono video virtual address. */
77:
78: #define PTABLE0_P 0x00001 /* Page directory physical address. */
79: #define PBASE 0x00002 /* Start of kernel, physical address. */
80:
81: #define PTABLE0_V 0xFFFFE /* Page directory virtual address. */
82: #define PPTABLE1_V 0xFFFFC /* Virtual address of the page table
83: * for the virtual page table.
84: */
85: #define WORK1 0xFFFFB /* Scratch page 1 virtual address. */
86: #define WORK0 0xFFFFA /* Scratch page 0 virtual address. */
87:
88: #define MAX_VADDR ctob(VIDEOb) /* Highest allocatable virtual address. */
89: /*
90: * Addresses in kernel data for the RAM disk are now in rm.c.
91: * As of 92/06/25, they are
92: * RAM0 0x80000 Ram disk 0 virtual click address.
93: * RAM1 0x80800 Ram disk 1 virtual click address.
94: * RAMSIZE 0x00800 Number of clicks in each ram disk.
95: */
96:
97: #define SBASE 0xFFC00 /* Start of kernel, virtual address. */
98: #define PTABLE1_V 0xFF800 /* Start of virtual page table. */
99:
100: /*
101: * ptable0_v[] is the page directory (master page table).
102: * ptable1_v[] is the virtual page table.
103: */
104: #define ptable0_v ((long *)ctob(PTABLE0_V))
105: #define ptable1_v ((long *)ctob(PTABLE1_V))
106:
107:
108: #define SZDT 8 /* size of a segment descriptor */
109:
110: #define clickseg(n) (((long)n) << BPCSHIFT)
111: #define segclick(n) ((long)(n) >> BPCSHIFT)
112:
113: #define regread(n) ptable0_v[(n)>>BPC1SHIFT]
114: #define regload(n, v) { ptable0_v[(n)>>BPC1SHIFT] = v; mmuupd(); }
115:
116: #define maparea(v) \
117: { ptable1_v[WORK0-SBASE] = clickseg(v) | SEG_SRW; mmuupd(); }
118:
119: #define xmode(ty) ((u.u_regl[DS]&0xffff) \
120: == ((ty)==286 ? (SEG_286_UD|R_USR) : (SEG_386_UD|R_USR)))
121: #define XMODE_286 ((u.u_regl[DS]&0xffff) == (SEG_286_UD|R_USR))
122: #define XMODE_386 ((u.u_regl[DS]&0xffff) == (SEG_386_UD|R_USR))
123: #define wdsize() ((XMODE_286) ? sizeof(short) : sizeof(int))
124:
125: /*
126: * These macros assume segment size <= 4 megabytes.
127: *
128: * MAPIO:absolute page table address, offset ->
129: * relative page table click# (20 bits) ... offset (12 bits)
130: * MAPIO converts (SEG.s_vmem, byte offset) to system global addr.
131: */
132: #define MAPIO(seg, off) (((seg)+((int)(off)>>BPCSHIFT) - sysmem.u.pbase) << \
133: BPCSHIFT | ((off) & (NBPC-1)))
134: #define P2P(addr) ((sysmem.u.pbase[btocrd(addr)]&~(NBPC-1)) |(addr&(NBPC-1)))
135:
136: #define BUDDY(addr,size) ((addr) ^ (1 << (size)))
137: #define NBUDDY 12 /* segments of 2^NBUDDY 4 click chunks (16 megabytes) */
138: #define SPLASH 3
139: #define NDATA 4 /* process data segments */
140: #define BLKSZ 2 /* log2 sizeof(BLOCKLIST)/sizeof(cseg_t) */
141: SR *loaded();
142: cseg_t *c_begin();
143:
144: #define INSERT2(t, p, pp) { \
145: (p)->forw = (pp); \
146: (p)->back = (pp)->back; \
147: (pp)->back->forw = (p); \
148: (pp)->back= (p); \
149: }
150:
151: #define DELETE2(p) ((p)->forw->back = (p)->back, (p)->back->forw = \
152: (p)->forw, (p)->forw = (p)->back = (p))
153:
154: #define INIT2(lp) ((lp)->forw = (lp)->back = (lp))
155:
156: typedef struct blocklist
157: {
158: struct blocklist *back;
159: struct blocklist *forw;
160: int kval;
161: int fill; /* sizeof(BLOCKLIST) :: power of 2 */
162: } BLOCKLIST;
163:
164: #define WCOUNT 32 /* number of bits in an int */
165: #define WSHIFT 5
166:
167: typedef struct {
168: union {
169: BLOCKLIST *budtab;
170: cseg_t *pbase;
171: } u; /* beginning of pointer area */
172: int budfree[1 << (NBUDDY-WSHIFT)];
173: BLOCKLIST bfree[NBUDDY];
174: unsigned short *tfree, *efree, *pfree;
175: /* vector of page descriptors (base, end, current pointer) */
176: unsigned short lo, hi; /* valid physical memory (min,max) */
177: vaddr_t vaddre; /* end of system */
178: } SYSMEM;
179:
180: extern SYSMEM sysmem;
181: cseg_t *c_alloc();
182: cseg_t *c_extend();
183: BLOCKLIST *arealloc();
184:
185: /*
186: * Declare and initialize an in-memory segment structure.
187: */
188: #define MAKESR(sr, seg) SEG seg; SR sr = { 0, 0, 0, &seg }
189: /*
190: * Is 'p' a valid physical click address?
191: */
192: #define pvalid(p) ((p) >= sysmem.lo && (p) < sysmem.hi)
193: /*
194: * How many physical clicks are free for allocation?
195: */
196: #define allocno() (sysmem.pfree - sysmem.tfree)
197:
198: /*
199: * IS_POW2() works for negative n only if the CPU uses 2's complement.
200: */
201: #define IS_POW2(n) (!((n) & ((n) - 1))) /* Is n a power of 2? */
202:
203: typedef struct {
204: int pid;
205: int r[SS+1];
206: int (*func)();
207: int a[5];
208: int res;
209: int err;
210: } EVENT;
211: #define NEV 32
212: extern EVENT evtab[NEV];
213: EVENT *evtrap();
214:
215: #else /* From here to EOF is for 286 kernels. */
216:
217: /*
218: * The following macros facilitate independent access
219: * to the selector and offset of a faddr_t (far *) pointer.
220: */
221: #define FP_OFF(f) ( ((unsigned short *) &(f))[0] )
222: #define FP_SEL(f) ( ((unsigned short *) &(f))[1] )
223:
224: #ifdef KERNEL
225: /*
226: * The following selector accesses the global descriptor table.
227: */
228: extern saddr_t gdtsel;
229:
230: /*
231: * The following functions manipulate virtual address translation tables.
232: */
233: extern faddr_t ptov(); /* faddr_t ptov( paddr_t, fsize_t ); */
234: extern faddr_t ptovx(); /* faddr_t ptovx( paddr_t ); */
235: extern paddr_t vtop(); /* paddr_t vtop( faddr_t ); */
236: extern void vrelse(); /* void vrelse( faddr_t ); */
237: extern void vremap(); /* void vremap( SEG * ); */
238: #endif /* KERNEL */
239:
240: #endif /* _I386 */
241:
242: #endif /* MMU_H */
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