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1.1 root 1: 37 \fBaaa\fR Adjust after addition
2: d5 0a \fBaad\fR Adjust AX before division
3: d4 0a \fBaam\fR Adjust AX after multiply
4: 3f \fBaas\fR Adjust AL after subtraction
5: .sp \n(pDu
6: \fBadc\fR Add with carry
7: 83 /2 \fBadcl\fR \fIimm8s,rm32\fR
8: 83 /2 \fBadcw\fR \fIimm8s,rm16\fR
9: 14 \fBadcb\fR \fIimm8,al\fR
10: 15 \fBadcw\fR \fIimm16,ax\fR
11: 15 \fBadcl\fR \fIimm32,eax\fR
12: 15 \fBadcl\fR \fIimm32\fR
13: 80 /2 \fBadcb\fR \fIimm8,rm8\fR
14: 81 /2 \fBadcw\fR \fIimm16,rm16\fR
15: 81 /2 \fBadcl\fR \fIimm32,rm32\fR
16: 12 /r \fBadcb\fR \fIrm8,r8\fR
17: 13 /r \fBadcw\fR \fIrm16,r16\fR
18: 13 /r \fBadcl\fR \fIrm32,r32\fR
19: 10 /r \fBadcb\fR \fIr8,rm8\fR
20: 11 /r \fBadcw\fR \fIr16,rm16\fR
21: 11 /r \fBadcl\fR \fIr32,rm32\fR
22: .sp \n(pDu
23: \fBadd\fR Add
24: 83 /0 \fBaddl\fR \fIimm8s,rm32\fR
25: 83 /0 \fBaddw\fR \fIimm8s,rm16\fR
26: 04 \fBaddb\fR \fIimm8,al\fR
27: 05 \fBaddw\fR \fIimm16,ax\fR
28: 05 \fBaddl\fR \fIimm32,eax\fR
29: 05 \fBaddl\fR \fIimm32\fR
30: 80 /0 \fBaddb\fR \fIimm8,rm8\fR
31: 81 /0 \fBaddw\fR \fIimm16,rm16\fR
32: 81 /0 \fBaddl\fR \fIimm32,rm32\fR
33: 02 /r \fBaddb\fR \fIrm8,r8\fR
34: 03 /r \fBaddw\fR \fIrm16,r16\fR
35: 03 /r \fBaddl\fR \fIrm32,r32\fR
36: 00 /r \fBaddb\fR \fIr8,rm8\fR
37: 01 /r \fBaddw\fR \fIr16,rm16\fR
38: 01 /r \fBaddl\fR \fIr32,rm32\fR
39: .sp \n(pDu
40: \fBand\fR Logical AND
41: 83 /4 \fBandl\fR \fIimm8s,rm32\fR
42: 83 /4 \fBandw\fR \fIimm8s,rm16\fR
43: 24 \fBandb\fR \fIimm8,al\fR
44: 25 \fBandw\fR \fIimm16,ax\fR
45: 25 \fBandl\fR \fIimm32,eax\fR
46: 25 \fBandl\fR \fIimm32\fR
47: 80 /4 \fBandb\fR \fIimm8,rm8\fR
48: 81 /4 \fBandw\fR \fIimm16,rm16\fR
49: 81 /4 \fBandl\fR \fIimm32,rm32\fR
50: 22 /r \fBandb\fR \fIrm8,r8\fR
51: 23 /r \fBandw\fR \fIrm16,r16\fR
52: 23 /r \fBandl\fR \fIrm32,r32\fR
53: 20 /r \fBandb\fR \fIr8,rm8\fR
54: 21 /r \fBandw\fR \fIr16,rm16\fR
55: 21 /r \fBandl\fR \fIr32,rm32\fR
56: .sp \n(pDu
57: 63 /r \fBarpl\fR \fIr16,rm16\fR Adjust RPL field of selector
58: .sp \n(pDu
59: \fBbound\fR Check if register is within bounds
60: 62 /r \fBboundw\fR \fIm16,r16\fR
61: 62 /r \fBboundl\fR \fIm32,r32\fR
62: .sp \n(pDu
63: \fBbsf\fR Bit scan forward
64: 0F bc \fBbsfw\fR \fIrm16,r16\fR
65: 0F bc \fBbsfl\fR \fIrm32,r32\fR
66: .sp \n(pDu
67: \fBbsr\fR Bit scan reverse
68: 0F bd \fBbsrw\fR \fIrm16,r16\fR
69: 0F bd \fBbsrl\fR \fIrm32,r32\fR
70: .sp \n(pDu
71: \fBbt\fR Save bit in carry flag
72: 0F a3 \fBbtw\fR \fIr16,rm16\fR
73: 0F a3 \fBbtl\fR \fIr32,rm32\fR
74: 0F ba /4 \fBbtw\fR \fIimm8,rm16\fR
75: 0F ba /4 \fBbtl\fR \fIimm8,rm32\fR
76: .sp \n(pDu
77: \fBbtc\fR Bit test and complement
78: 0F bb \fBbtcw\fR \fIr16,rm16\fR
79: 0F bb \fBbtcl\fR \fIr32,rm32\fR
80: 0F ba /7 \fBbtcw\fR \fIimm8,rm16\fR
81: 0F ba /7 \fBbtcl\fR \fIimm8,rm32\fR
82: .sp \n(pDu
83: \fBbtr\fR Bit test and reset
84: 0F b3 \fBbtrw\fR \fIr16,rm16\fR
85: 0F b3 \fBbtrl\fR \fIr32,rm32\fR
86: 0F ba /6 \fBbtrw\fR \fIimm8,rm16\fR
87: 0F ba /6 \fBbtrl\fR \fIimm8,rm32\fR
88: .sp \n(pDu
89: \fBbts\fR Bit test and set
90: 0F ab \fBbtsw\fR \fIr16,rm16\fR
91: 0F ab \fBbtsl\fR \fIr32,rm32\fR
92: 0F ba /5 \fBbtsw\fR \fIimm8,rm16\fR
93: 0F ba /5 \fBbtsl\fR \fIimm8,rm32\fR
94: .sp \n(pDu
95: e8 \fBcall\fR \fIreli\fR Call Procedure
96: 98 \fBcbtw\fR Sign extend AL
97: 98 \fBcbw\fR Sign extend AL
98: 99 \fBcdq\fR Double word to quad word
99: f8 \fBclc\fR Clear carry
100: fc \fBcld\fR Clear direction Flag
101: fa \fBcli\fR Clear interrupt Flag
102: 99 \fBcltd\fR Double word to quad word
103: 0F 06 \fBclts\fR Clear task-switched flag in CR0
104: f5 \fBcmc\fR Complement carry flag
105: .sp \n(pDu
106: \fBcmp\fR Compare
107: 83 /7 \fBcmpl\fR \fIimm8s,rm32\fR
108: 83 /7 \fBcmpw\fR \fIimm8s,rm16\fR
109: 3c \fBcmpb\fR \fIimm8,al\fR
110: 3d \fBcmpw\fR \fIimm16,ax\fR
111: 3d \fBcmpl\fR \fIimm32,eax\fR
112: 3d \fBcmpl\fR \fIimm32\fR
113: 80 /7 \fBcmpb\fR \fIimm8,rm8\fR
114: 81 /7 \fBcmpw\fR \fIimm16,rm16\fR
115: 81 /7 \fBcmpl\fR \fIimm32,rm32\fR
116: 3a /r \fBcmpb\fR \fIrm8,r8\fR
117: 3b /r \fBcmpw\fR \fIrm16,r16\fR
118: 3b /r \fBcmpl\fR \fIrm32,r32\fR
119: 38 /r \fBcmpb\fR \fIr8,rm8\fR
120: 39 /r \fBcmpw\fR \fIr16,rm16\fR
121: 39 /r \fBcmpl\fR \fIr32,rm32\fR
122: .sp \n(pDu
123: a6 \fBcmpsb\fR Compare bytes
124: a7 \fBcmpsl\fR Compare long
125: a7 \fBcmpsw\fR Compare words
126: 99 \fBcwd\fR Word to double word
127: 98 \fBcwde\fR Sign extend AX
128: 99 \fBcwtd\fR Word to double word
129: 98 \fBcwtl\fR Sign extend AX
130: 27 \fBdaa\fR Decimal adjust after addition
131: 2f \fBdas\fR Decimal adjust after subtraction
132: .sp \n(pDu
133: \fBdec\fR Decrement by 1
134: 48 +r \fBdecw\fR \fIr16\fR
135: 48 +r \fBdecl\fR \fIr32\fR
136: fe /1 \fBdecb\fR \fIrm8\fR
137: ff /1 \fBdecw\fR \fIrm16\fR
138: ff /1 \fBdecl\fR \fIrm32\fR
139: .sp \n(pDu
140: \fBdiv\fR Unsigned divide
141: f6 /6 \fBdivb\fR \fIrm8,al\fR
142: f6 /6 \fBdivb\fR \fIrm8\fR
143: f7 /6 \fBdivw\fR \fIrm16,ax\fR
144: f7 /6 \fBdivw\fR \fIrm16\fR
145: f7 /6 \fBdivl\fR \fIrm32,eax\fR
146: f7 /6 \fBdivl\fR \fIrm32\fR
147: .sp \n(pDu
148: c8 \fBenter\fR \fIimm8,imm16\fR Make stack frame for procedure
149: d9 f0 \fBf2xm1\fR ST = 2 ** ST - 1
150: d9 e1 \fBfabs\fR ST = abs(ST)
151: .sp \n(pDu
152: \fBfadd\fR Floating add
153: d8 /0 \fBfadds\fR \fIm32\fR
154: dc /0 \fBfaddl\fR \fIm64\fR
155: d8 c0 +r \fBfadd\fR \fIfpreg,st0\fR
156: d8 c0 +r \fBfadd\fR \fIfpreg\fR
157: de c1 \fBfadd\fR
158: dc c0 +r \fBfadd\fR \fIst0,fpreg\fR
159: .sp \n(pDu
160: \fBfaddp\fR Floating add and pop
161: de c0 +r \fBfaddp\fR \fIst0,fpreg\fR
162: de c0 +r \fBfaddp\fR \fIfpreg\fR
163: de c1 \fBfaddp\fR
164: .sp \n(pDu
165: df /4 \fBfbld\fR \fIm80\fR Load Binary Coded Decimal
166: df /6 \fBfbstp\fR \fIm80\fR Store Binary Coded Decimal and Pop
167: d9 e0 \fBfchs\fR Change Floating Sign
168: 9B db e2 \fBfclex\fR Clear floating point exception flags
169: .sp \n(pDu
170: \fBfcom\fR Floating Compare
171: d8 /2 \fBfcoms\fR \fIm32\fR
172: dc /2 \fBfcoml\fR \fIm64\fR
173: d8 d0 +r \fBfcom\fR \fIfpreg,st0\fR
174: d8 d0 +r \fBfcom\fR \fIfpreg\fR
175: d8 d1 \fBfcom\fR
176: .sp \n(pDu
177: \fBfcomp\fR Floating Compare and Pop
178: d8 /3 \fBfcomps\fR \fIm32\fR
179: dc /3 \fBfcompl\fR \fIm64\fR
180: d8 d8 +r \fBfcomp\fR \fIfpreg\fR
181: d8 d9 \fBfcomp\fR
182: .sp \n(pDu
183: de d9 \fBfcompp\fR Floating Compare and pop twice
184: d9 ff \fBfcos\fR Cosine
185: d9 f6 \fBfdecstp\fR Decrement Stack Top Pointer
186: .sp \n(pDu
187: \fBfdiv\fR Floating divide
188: d8 /6 \fBfdivs\fR \fIm32\fR
189: dc /6 \fBfdivl\fR \fIm64\fR
190: d8 f0 +r \fBfdiv\fR \fIfpreg,st0\fR
191: d8 f0 +r \fBfdiv\fR \fIfpreg\fR
192: de f1 \fBfdiv\fR
193: dc f0 +r \fBfdiv\fR \fIst0,fpreg\fR
194: .sp \n(pDu
195: \fBfdivp\fR Floating divide and pop
196: de f0 +r \fBfdivp\fR \fIst0,fpreg\fR
197: de f0 +r \fBfdivp\fR \fIfpreg\fR
198: de f1 \fBfdivp\fR
199: .sp \n(pDu
200: \fBfdivr\fR Reverse floating divide
201: d8 /7 \fBfdivrs\fR \fIm32\fR
202: dc /7 \fBfdivrl\fR \fIm64\fR
203: d8 f8 +r \fBfdivr\fR \fIfpreg,st0\fR
204: d8 f8 +r \fBfdivr\fR \fIfpreg\fR
205: de f9 \fBfdivr\fR
206: dc f8 +r \fBfdivr\fR \fIst0,fpreg\fR
207: .sp \n(pDu
208: \fBfdivrp\fR Reverse floating divide and pop
209: de f8 +r \fBfdivrp\fR \fIst0,fpreg\fR
210: de f8 +r \fBfdivrp\fR \fIfpreg\fR
211: de f9 \fBfdivrp\fR
212: .sp \n(pDu
213: dd c0 +r \fBffree\fR \fIfpreg\fR Free Floating Point Register
214: .sp \n(pDu
215: \fBfiadd\fR Add integer to float
216: da /0 \fBfiaddl\fR \fIm32\fR
217: de /0 \fBfiadds\fR \fIm16\fR
218: .sp \n(pDu
219: \fBficom\fR Compare float to integer
220: da /2 \fBficoml\fR \fIm32\fR
221: de /2 \fBficoms\fR \fIm16\fR
222: .sp \n(pDu
223: \fBficomp\fR Compare float to integer and pop
224: da /3 \fBficompl\fR \fIm32\fR
225: de /3 \fBficomps\fR \fIm16\fR
226: .sp \n(pDu
227: \fBfidiv\fR Divide float by integer
228: da /6 \fBfidivl\fR \fIm32\fR
229: de /6 \fBfidivs\fR \fIm16\fR
230: .sp \n(pDu
231: \fBfidivr\fR Reverse divide integer by float
232: da /7 \fBfidivrl\fR \fIm32\fR
233: de /7 \fBfidivrs\fR \fIm16\fR
234: .sp \n(pDu
235: \fBfild\fR Load integer
236: db /0 \fBfildl\fR \fIm32\fR
237: df /0 \fBfilds\fR \fIm16\fR
238: df /5 \fBfildll\fR \fIm64\fR
239: .sp \n(pDu
240: \fBfimul\fR Multiply integer to float
241: da /1 \fBfimull\fR \fIm32\fR
242: de /1 \fBfimuls\fR \fIm16\fR
243: .sp \n(pDu
244: d9 f7 \fBfincstp\fR Increment Stack Top Pointer
245: 9B db e3 \fBfinit\fR Initialize Floating Point Unit
246: .sp \n(pDu
247: \fBfist\fR Store integer
248: db /2 \fBfistl\fR \fIm32\fR
249: df /2 \fBfists\fR \fIm16\fR
250: .sp \n(pDu
251: \fBfistp\fR Store integer and pop
252: db /3 \fBfistpl\fR \fIm32\fR
253: df /3 \fBfistps\fR \fIm16\fR
254: df /7 \fBfistpll\fR \fIm32\fR
255: .sp \n(pDu
256: \fBfisub\fR Subtract integer from float
257: da /4 \fBfisubl\fR \fIm32\fR
258: de /4 \fBfisubs\fR \fIm16\fR
259: .sp \n(pDu
260: \fBfisubr\fR Reverse subtract integer from float
261: da /5 \fBfisubrl\fR \fIm32\fR
262: de /5 \fBfisubrs\fR \fIm16\fR
263: .sp \n(pDu
264: \fBfld\fR Load Real
265: d9 c0 +r \fBfld\fR \fIfpreg\fR
266: d9 /0 \fBflds\fR \fIm32\fR
267: dd /0 \fBfldl\fR \fIm32\fR
268: db /5 \fBfldt\fR \fIm64\fR
269: .sp \n(pDu
270: d9 e8 \fBfld1\fR Load Constant 1
271: d9 /5 \fBfldcw\fR \fIm32\fR Load Floating Point Control Word
272: d9 /4 \fBfldenv\fR \fIm32\fR Load FPU Environment
273: d9 ea \fBfldl2e\fR Load Constant log(e) base 2
274: d9 e9 \fBfldl2t\fR Load Constant log(10) base 2
275: d9 ec \fBfldlg2\fR Load Constant log(2) base 10
276: d9 ed \fBfldln2\fR Load Constant log(2) base e
277: d9 eb \fBfldpi\fR Load Constant pi
278: d9 ee \fBfldz\fR Load Constant 0.0
279: .sp \n(pDu
280: \fBfmul\fR Floating multiply
281: d8 /1 \fBfmuls\fR \fIm32\fR
282: dc /1 \fBfmull\fR \fIm64\fR
283: d8 c8 +r \fBfmul\fR \fIfpreg,st0\fR
284: d8 c8 +r \fBfmul\fR \fIfpreg\fR
285: de c9 \fBfmul\fR
286: dc c8 +r \fBfmul\fR \fIst0,fpreg\fR
287: .sp \n(pDu
288: \fBfmulp\fR Floating multiply and pop
289: de c8 +r \fBfmulp\fR \fIst0,fpreg\fR
290: de c8 +r \fBfmulp\fR \fIfpreg\fR
291: de c9 \fBfmulp\fR
292: .sp \n(pDu
293: db e2 \fBfnclex\fR Clear floating point exception flags no wait
294: db e3 \fBfninit\fR Initialize Floating Point Unit no wait
295: d9 d0 \fBfnop\fR No Operation
296: dd /6 \fBfnsave\fR \fIm32\fR Store FPU State no wait
297: d9 /7 \fBfnstcw\fR \fIm32\fR Store Control Word no wait
298: d9 /6 \fBfnstenv\fR \fIm32\fR Store FPU Environment no wait
299: .sp \n(pDu
300: \fBfnstsw\fR Store Status Word no wait
301: dd /7 \fBfnstsw\fR \fIm16\fR
302: df e0 \fBfnstsw\fR \fIax\fR
303: .sp \n(pDu
304: d9 f3 \fBfpatan\fR Partial Arctangent
305: d9 f8 \fBfprem\fR Partial Remainder toward 0
306: d9 f5 \fBfprem1\fR Partial Remainder < 1/2 modulus
307: d9 f2 \fBfptan\fR Partial Tangent
308: d9 fc \fBfrndint\fR Round To Integer
309: dd /4 \fBfrstor\fR \fIm32\fR Resore FPU State
310: db f4 \fBfrstpm\fR set 287XL real mode (nop for 387/486)
311: 9B dd /6 \fBfsave\fR \fIm32\fR Store FPU State
312: d9 fd \fBfscale\fR Scale
313: db e4 \fBfsetpm\fR set 287 protected mode (nop for 387/486)
314: d9 fe \fBfsin\fR Sine
315: d9 fb \fBfsincos\fR Sine and Cosine
316: d9 fa \fBfsqrt\fR Square Root
317: .sp \n(pDu
318: \fBfst\fR Store Real
319: dd d0 +r \fBfst\fR \fIfpreg\fR
320: d9 /2 \fBfsts\fR \fIm32\fR
321: dd /2 \fBfstl\fR \fIm64\fR
322: .sp \n(pDu
323: 9B d9 /7 \fBfstcw\fR \fIm32\fR Store Control Word
324: 9B d9 /6 \fBfstenv\fR \fIm32\fR Store FPU Environment
325: .sp \n(pDu
326: \fBfstp\fR Store Real and pop
327: dd d8 +r \fBfstp\fR \fIfpreg\fR
328: d9 /3 \fBfstps\fR \fIm32\fR
329: dd /3 \fBfstpl\fR \fIm64\fR
330: db /7 \fBfstpt\fR \fIm80\fR
331: .sp \n(pDu
332: \fBfstsw\fR Store Status Word
333: 9B dd /7 \fBfstsw\fR \fIm16\fR
334: 9B df e0 \fBfstsw\fR \fIax\fR
335: .sp \n(pDu
336: \fBfsub\fR Floating subtract
337: d8 /4 \fBfsubs\fR \fIm32\fR
338: dc /4 \fBfsubl\fR \fIm64\fR
339: d8 e0 +r \fBfsub\fR \fIfpreg,st0\fR
340: d8 e0 +r \fBfsub\fR \fIfpreg\fR
341: de e1 \fBfsub\fR
342: dc e0 +r \fBfsub\fR \fIst0,fpreg\fR
343: .sp \n(pDu
344: \fBfsubp\fR Floating subtract and pop
345: de e0 +r \fBfsubp\fR \fIst0,fpreg\fR
346: de e0 +r \fBfsubp\fR \fIfpreg\fR
347: de e1 \fBfsubp\fR
348: .sp \n(pDu
349: \fBfsubr\fR Reverse floating subtract
350: d8 /5 \fBfsubrs\fR \fIm32\fR
351: dc /5 \fBfsubrl\fR \fIm64\fR
352: d8 e8 +r \fBfsubr\fR \fIfpreg,st0\fR
353: d8 e8 +r \fBfsubr\fR \fIfpreg\fR
354: de e9 \fBfsubr\fR
355: dc e8 +r \fBfsubr\fR \fIst0,fpreg\fR
356: .sp \n(pDu
357: \fBfsubrp\fR Reverse floating subtract and pop
358: de e8 +r \fBfsubrp\fR \fIst0,fpreg\fR
359: de e8 +r \fBfsubrp\fR \fIfpreg\fR
360: de e9 \fBfsubrp\fR
361: .sp \n(pDu
362: d9 e4 \fBftst\fR Test
363: .sp \n(pDu
364: \fBfucom\fR Unordered compare real
365: dd e0 +r \fBfucom\fR \fIst0,fpreg\fR
366: dd e0 +r \fBfucom\fR \fIfpreg\fR
367: dd e1 \fBfucom\fR
368: .sp \n(pDu
369: \fBfucomp\fR Unordered compare real and pop
370: dd e8 +r \fBfucomp\fR \fIst0,fpreg\fR
371: dd e8 +r \fBfucomp\fR \fIfpreg\fR
372: dd e9 \fBfucomp\fR
373: .sp \n(pDu
374: da e9 \fBfucompp\fR Unordered compare %st %st1 and pop twice
375: 9b \fBfwait\fR Wait for coprocessor
376: d9 e5 \fBfxam\fR Examine
377: .sp \n(pDu
378: \fBfxch\fR Floating exchange
379: d9 c8 +r \fBfxch\fR \fIst0,fpreg\fR
380: d9 c8 +r \fBfxch\fR \fIfpreg,st0\fR
381: d9 c8 +r \fBfxch\fR \fIfpreg\fR
382: d9 c9 \fBfxch\fR
383: .sp \n(pDu
384: d9 f4 \fBfxtract\fR Extract Exponent and Significand
385: d9 f1 \fBfyl2x\fR %st1 * log(%st) base 2
386: d9 f9 \fBfyl2xp1\fR %st1 * log(%st + 1.0) base 2
387: f4 \fBhlt\fR Halt
388: ff /2 \fBicall\fR \fIrm32\fR Call indirect
389: .sp \n(pDu
390: \fBidiv\fR Signed divide
391: f6 /7 \fBidivb\fR \fIrm8,al\fR
392: f6 /7 \fBidivb\fR \fIrm8\fR
393: f7 /7 \fBidivw\fR \fIrm16,ax\fR
394: f7 /7 \fBidivw\fR \fIrm16\fR
395: f7 /7 \fBidivl\fR \fIrm32,eax\fR
396: f7 /7 \fBidivl\fR \fIrm32\fR
397: .sp \n(pDu
398: ff /4 \fBijmp\fR \fIrm32\fR Jump indirect
399: ff /3 \fBilcall\fR \fIm32\fR Long call indirect
400: ff /5 \fBiljmp\fR \fIm32\fR Long jump indirect
401: .sp \n(pDu
402: \fBimul\fR Signed multiply
403: f6 /5 \fBimulb\fR \fIrm8\fR
404: f7 /5 \fBimulw\fR \fIrm16\fR
405: f7 /5 \fBimull\fR \fIrm32\fR
406: 0F af /r \fBimulw\fR \fIrm16,r16\fR
407: 0F af /r \fBimull\fR \fIrm32,r32\fR
408: 6b \fBimulw\fR \fIimm8s,rm16,r16\fR
409: 6b \fBimull\fR \fIimm8s,rm32,r32\fR
410: 6b /r \fBimulw\fR \fIimm8s,r16\fR
411: 6b /r \fBimull\fR \fIimm8s,r32\fR
412: 69 \fBimulw\fR \fIimm16,rm16,r16\fR
413: 69 \fBimull\fR \fIimm32,rm32,r32\fR
414: 69 /r \fBimulw\fR \fIimm16,r16\fR
415: 69 /r \fBimull\fR \fIimm32,r32\fR
416: .sp \n(pDu
417: \fBin\fR Input from port
418: ec \fBin\fR \fIdx,al\fR
419: ed \fBin\fR \fIdx,ax\fR
420: ed \fBin\fR \fIdx,eax\fR
421: e4 \fBinb\fR \fIimm8\fR
422: e5 \fBinw\fR \fIimm8\fR
423: e5 \fBinl\fR \fIimm8\fR
424: ec \fBinb\fR \fI(dx)\fR
425: ed \fBinw\fR \fI(dx)\fR
426: ed \fBinl\fR \fI(dx)\fR
427: .sp \n(pDu
428: \fBinc\fR Increment by one
429: 40 +r \fBincw\fR \fIr16\fR
430: 40 +r \fBincl\fR \fIr32\fR
431: fe /0 \fBincb\fR \fIrm8\fR
432: ff /0 \fBincw\fR \fIrm16\fR
433: ff /0 \fBincl\fR \fIrm32\fR
434: .sp \n(pDu
435: 6c \fBinsb\fR Input byte from port into ES:(E)DI
436: 6c \fBinsb\fR \fI(dx)\fR Input byte from port into ES:(E)DI
437: 6d \fBinsl\fR Input long from port into ES:(E)DI
438: 6d \fBinsl\fR \fI(dx)\fR Input long from port into ES:(E)DI
439: 6d \fBinsw\fR Input word from port into ES:(E)DI
440: 6d \fBinsw\fR \fI(dx)\fR Input word from port into ES:(E)DI
441: cc \fBint\fR \fIcon3\fR Interrupt 3
442: cd \fBint\fR \fIimm8\fR Interrupt
443: ce \fBinto\fR Int 4 if overflow is 1
444: cf \fBiret\fR Interrupt return
445: cf \fBiretd\fR Different mode different opcode ?
446: 07 \fBja\fR \fIreli\fR Jump if above
447:
448: 03 \fBjae\fR \fIreli\fR Jump if above or equal
449: 02 \fBjb\fR \fIreli\fR Jump if below
450: 06 \fBjbe\fR \fIreli\fR Jump if below or equal
451: 02 \fBjc\fR \fIreli\fR Jump if carry
452: e3 \fBjcxz\fR \fIrel8\fR Jump if CX is zero
453: 04 \fBje\fR \fIreli\fR Jump if equal
454: e3 \fBjecxz\fR \fIrel8\fR Jump if CX is zero
455:
456: 0f \fBjg\fR \fIreli\fR Jump if greater
457: 0d \fBjge\fR \fIreli\fR Jump if greater or equal
458: 0c \fBjl\fR \fIreli\fR Jump if less
459: 0e \fBjle\fR \fIreli\fR Jump if less or equal
460: e9 \fBjmp\fR \fIreli\fR Jump absolute
461: 06 \fBjna\fR \fIreli\fR Jump if not above
462: 02 \fBjnae\fR \fIreli\fR Jump if not above or equal
463: 03 \fBjnb\fR \fIreli\fR Jump if not below
464: 07 \fBjnbe\fR \fIreli\fR Jump if not below or equal
465: 03 \fBjnc\fR \fIreli\fR Jump if no carry
466: 05 \fBjne\fR \fIreli\fR Jump if not equal
467: 0e \fBjng\fR \fIreli\fR Jump if not greater
468: 0c \fBjnge\fR \fIreli\fR Jump if not greater or equal
469: 0d \fBjnl\fR \fIreli\fR Jump if not less
470: 0f \fBjnle\fR \fIreli\fR Jump if not less or equal
471: 01 \fBjno\fR \fIreli\fR Jump if not overflow
472: 0b \fBjnp\fR \fIreli\fR Jump if not parity
473: 09 \fBjns\fR \fIreli\fR Jump if not sign
474: 05 \fBjnz\fR \fIreli\fR Jump if not zero
475: 00 \fBjo\fR \fIreli\fR Jump if overflow
476: 0a \fBjp\fR \fIreli\fR Jump if parity
477: 0a \fBjpe\fR \fIreli\fR Jump if parity even
478: 0b \fBjpo\fR \fIreli\fR Jump if parity odd
479: 08 \fBjs\fR \fIreli\fR Jump if sign
480: 04 \fBjz\fR \fIreli\fR Jump if zero
481: 04 \fBjz\fR \fIreli\fR Jump if zero
482: 9f \fBlahf\fR Load flags into AH register
483: .sp \n(pDu
484: \fBlar\fR Load access rights byte
485: 0F 02 /r \fBlarw\fR \fIrm16,r16\fR
486: 0F 02 /r \fBlarl\fR \fIrm32,r32\fR
487: .sp \n(pDu
488: 9a \fBlcall\fR \fIimm16x,imm32\fR Long call
489: .sp \n(pDu
490: \fBlds\fR load full pointer DS:r16
491: c5 /r \fBldsw\fR \fIm16,r16\fR
492: c5 /r \fBldsl\fR \fIm32,r32\fR
493: .sp \n(pDu
494: \fBlea\fR Load effective address
495: 8d /r \fBleaw\fR \fIm16,r16\fR
496: 8d /r \fBleal\fR \fIm32,r32\fR
497: .sp \n(pDu
498: c9 \fBleave\fR High level procedure exit
499: .sp \n(pDu
500: \fBles\fR Load full pointer ES:r16
501: c4 /r \fBlesw\fR \fIm16,r16\fR
502: c4 /r \fBlesl\fR \fIm32,r32\fR
503: .sp \n(pDu
504: \fBlfs\fR Load full pointer FS:r16
505: 0F b4 /r \fBlfsw\fR \fIm16,r16\fR
506: 0F b4 /r \fBlfsl\fR \fIm32,r32\fR
507: .sp \n(pDu
508: \fBlgdt\fR Load m into DGTR
509: 0F 01 /2 \fBlgdtw\fR \fIm16\fR
510: 0F 01 /2 \fBlgdtl\fR \fIm32\fR
511: .sp \n(pDu
512: \fBlgs\fR Load full pointer GS:r16
513: 0F b5 /r \fBlgsw\fR \fIm16,r16\fR
514: 0F b5 /r \fBlgsl\fR \fIm32,r32\fR
515: .sp \n(pDu
516: \fBlidt\fR Load m into IDTR
517: 0F 01 /3 \fBlidtw\fR \fIm16\fR
518: 0F 01 /3 \fBlidtl\fR \fIm32\fR
519: .sp \n(pDu
520: ea \fBljmp\fR \fIimm16x,imm32\fR Long jump
521: 0F 00 /2 \fBlldt\fR \fIrm16\fR Load local descriptor table register
522: 0F 01 /6 \fBlmsw\fR \fIrm16\fR Load machine status word
523: f0 \fBlock\fR Assert lock signal for next instruction
524: ac \fBlodsb\fR Load string operand byte
525: ad \fBlodsl\fR Load string operand long
526: ad \fBlodsw\fR Load string operand word
527: e2 \fBloop\fR \fIrel8\fR Dec count jmp if count <> 0
528: e1 \fBloope\fR \fIrel8\fR Dec count jmp if count <> 0 and ZF = 1
529: e0 \fBloopne\fR \fIrel8\fR Dec count jmp if count <> 0 and ZF = 0
530: e0 \fBloopnz\fR \fIrel8\fR Dec count jmp if count <> 0 and ZF = 0
531: e1 \fBloopz\fR \fIrel8\fR Dec count jmp if count <> 0 and ZF = 1
532: cb \fBlret\fR Far return
533: ca \fBlret\fR \fIimm16\fR Far return pop imm16 bytes of parms
534: .sp \n(pDu
535: \fBlsl\fR Load segment limit
536: 0F 03 /r \fBlslw\fR \fIrm16,r16\fR
537: 0F 03 /r \fBlsll\fR \fIrm32,r32\fR
538: .sp \n(pDu
539: \fBlss\fR Load full pointer SS:r16
540: 0F b2 /r \fBlssw\fR \fIm16,r16\fR
541: 0F b2 /r \fBlssl\fR \fIm32,r32\fR
542: .sp \n(pDu
543: 0F 00 /3 \fBltr\fR \fIrm16\fR Load task register
544: .sp \n(pDu
545: \fBmov\fR Move data
546: a0 \fBmovb\fR \fImoffs,al\fR
547: a1 \fBmovw\fR \fImoffs,ax\fR
548: a1 \fBmovl\fR \fImoffs,eax\fR
549: a2 \fBmovb\fR \fIal,moffs\fR
550: a3 \fBmovw\fR \fIax,moffs\fR
551: a3 \fBmovl\fR \fIeax,moffs\fR
552: 8a /r \fBmovb\fR \fIrm8,r8\fR
553: 8b /r \fBmovw\fR \fIrm16,r16\fR
554: 8b /r \fBmovl\fR \fIrm32,r32\fR
555: 88 /r \fBmovb\fR \fIr8,rm8\fR
556: 89 /r \fBmovw\fR \fIr16,rm16\fR
557: 89 /r \fBmovl\fR \fIr32,rm32\fR
558: 8c /r \fBmovw\fR \fIsreg,rm16\fR
559: 8e /r \fBmovw\fR \fIrm16,sreg\fR
560: b0 +r \fBmovb\fR \fIimm8,r8\fR
561: b8 +r \fBmovw\fR \fIimm16,r16\fR
562: b8 +r \fBmovl\fR \fIimm32,r32\fR
563: c6 \fBmovb\fR \fIimm8,rm8\fR
564: c7 \fBmovw\fR \fIimm16,rm16\fR
565: c7 \fBmovl\fR \fIimm32,rm32\fR
566: 0F 20 /r \fBmovl\fR \fIctlreg,r32\fR
567: 0F 22 /r \fBmovl\fR \fIr32,ctlreg\fR
568: 0F 21 /r \fBmovl\fR \fIdbreg,r32\fR
569: 0F 23 /r \fBmovl\fR \fIr32,dbreg\fR
570: 0F 24 /r \fBmovl\fR \fItreg,r32\fR
571: 0F 26 /r \fBmovl\fR \fIr32,treg\fR
572: .sp \n(pDu
573: a4 \fBmovsb\fR Move bytes
574: a5 \fBmovsl\fR Move longs
575: a5 \fBmovsw\fR Move words
576: .sp \n(pDu
577: \fBmovsx\fR Move with sign extend
578: 0F be /r \fBmovsxb\fR \fIrm8,r16\fR
579: 0F be /r \fBmovsxb\fR \fIrm8,r32\fR
580: 0F bf /r \fBmovsxw\fR \fIrm16,r32\fR
581: 0F be /r \fBmovsbw\fR \fIrm8,r16\fR
582: 0F be /r \fBmovsbl\fR \fIrm8,r32\fR
583: 0F bf /r \fBmovswl\fR \fIrm16,r32\fR
584: .sp \n(pDu
585: \fBmovzx\fR Move with zero extend
586: 0F b6 /r \fBmovzxb\fR \fIrm8,r16\fR
587: 0F b6 /r \fBmovzxb\fR \fIrm8,r32\fR
588: 0F b7 /r \fBmovzxw\fR \fIrm16,r32\fR
589: 0F b6 /r \fBmovzbw\fR \fIrm8,r16\fR
590: 0F b6 /r \fBmovzbl\fR \fIrm8,r32\fR
591: 0F b7 /r \fBmovzwl\fR \fIrm16,r32\fR
592: .sp \n(pDu
593: \fBmul\fR Unsigned multiply
594: f6 /4 \fBmulb\fR \fIrm8,al\fR
595: f6 /4 \fBmulb\fR \fIrm8\fR
596: f7 /4 \fBmulw\fR \fIrm16,ax\fR
597: f7 /4 \fBmulw\fR \fIrm16\fR
598: f7 /4 \fBmull\fR \fIrm32,eax\fR
599: f7 /4 \fBmull\fR \fIrm32\fR
600: .sp \n(pDu
601: \fBneg\fR Negate
602: f6 /3 \fBnegb\fR \fIrm8\fR
603: f7 /3 \fBnegw\fR \fIrm16\fR
604: f7 /3 \fBnegl\fR \fIrm32\fR
605: .sp \n(pDu
606: 90 \fBnop\fR No operation
607: .sp \n(pDu
608: \fBnot\fR Invert bits
609: f6 /2 \fBnotb\fR \fIrm8\fR
610: f7 /2 \fBnotw\fR \fIrm16\fR
611: f7 /2 \fBnotl\fR \fIrm32\fR
612: .sp \n(pDu
613: \fBor\fR Logical inclusive OR
614: 83 /1 \fBorl\fR \fIimm8s,rm32\fR
615: 83 /1 \fBorw\fR \fIimm8s,rm16\fR
616: 0c \fBorb\fR \fIimm8,al\fR
617: 0d \fBorw\fR \fIimm16,ax\fR
618: 0d \fBorl\fR \fIimm32,eax\fR
619: 0d \fBorl\fR \fIimm32\fR
620: 80 /1 \fBorb\fR \fIimm8,rm8\fR
621: 81 /1 \fBorw\fR \fIimm16,rm16\fR
622: 81 /1 \fBorl\fR \fIimm32,rm32\fR
623: 0a /r \fBorb\fR \fIrm8,r8\fR
624: 0b /r \fBorw\fR \fIrm16,r16\fR
625: 0b /r \fBorl\fR \fIrm32,r32\fR
626: 08 /r \fBorb\fR \fIr8,rm8\fR
627: 09 /r \fBorw\fR \fIr16,rm16\fR
628: 09 /r \fBorl\fR \fIr32,rm32\fR
629: .sp \n(pDu
630: \fBout\fR Output from port
631: e6 \fBoutb\fR \fIimm8\fR
632: e7 \fBoutw\fR \fIimm8\fR
633: e7 \fBoutl\fR \fIimm8\fR
634: ee \fBoutb\fR \fI(dx)\fR
635: ef \fBoutw\fR \fI(dx)\fR
636: ef \fBoutl\fR \fI(dx)\fR
637: ee \fBout\fR \fIal,dx\fR
638: ef \fBout\fR \fIax,dx\fR
639: ef \fBout\fR \fIeax,dx\fR
640: .sp \n(pDu
641: 6e \fBoutsb\fR Output byte to port into ES:(E)DI
642: 6f \fBoutsl\fR Output long to port into ES:(E)DI
643: 6f \fBoutsw\fR Output word to port into ES:(E)DI
644: .sp \n(pDu
645: \fBpop\fR Pop a word from the stack
646: 58 +r \fBpopw\fR \fIr16\fR
647: 58 +r \fBpopl\fR \fIr32\fR
648: 1f \fBpopw\fR \fIds\fR
649: 07 \fBpopw\fR \fIes\fR
650: 17 \fBpopw\fR \fIss\fR
651: 0F a1 \fBpopw\fR \fIfs\fR
652: 0F a9 \fBpopw\fR \fIgs\fR
653: 8f /0 \fBpopw\fR \fIm16\fR
654: 8f /0 \fBpopl\fR \fIm32\fR
655: .sp \n(pDu
656: \fBpopa\fR Pop all
657: 61 \fBpopaw\fR
658: 61 \fBpopal\fR
659: .sp \n(pDu
660: \fBpopf\fR Pop stack into flags
661: 9d \fBpopfw\fR
662: 9d \fBpopfl\fR
663: .sp \n(pDu
664: \fBpush\fR Push a word on the stack
665: 50 +r \fBpushw\fR \fIr16\fR
666: 50 +r \fBpushl\fR \fIr32\fR
667: 6a \fBpushb\fR \fIimm8s\fR
668: 68 \fBpushw\fR \fIimm16\fR
669: 68 \fBpushl\fR \fIimm32\fR
670: 0e \fBpushw\fR \fIcs\fR
671: 1e \fBpushw\fR \fIds\fR
672: 06 \fBpushw\fR \fIes\fR
673: 16 \fBpushw\fR \fIss\fR
674: 0F a0 \fBpushw\fR \fIfs\fR
675: 0F a8 \fBpushw\fR \fIgs\fR
676: ff /6 \fBpushw\fR \fIm16\fR
677: ff /6 \fBpushl\fR \fIm32\fR
678: .sp \n(pDu
679: \fBpusha\fR Push all
680: 60 \fBpushaw\fR
681: 60 \fBpushal\fR
682: .sp \n(pDu
683: \fBpushf\fR Push flags
684: 9c \fBpushfw\fR
685: 9c \fBpushfl\fR
686: .sp \n(pDu
687: \fBrcl\fR Rotate carry left
688: d0 /2 \fBrclb\fR \fIcon1,rm8\fR
689: d0 /2 \fBrclb\fR \fIrm8\fR
690: d2 /2 \fBrclb\fR \fIcl,rm8\fR
691: c0 /2 \fBrclb\fR \fIimm8,rm8\fR
692: d1 /2 \fBrclw\fR \fIcon1,rm16\fR
693: d1 /2 \fBrclw\fR \fIrm16\fR
694: d3 /2 \fBrclw\fR \fIcl,rm16\fR
695: c1 /2 \fBrclw\fR \fIimm8,rm16\fR
696: d1 /2 \fBrcll\fR \fIcon1,rm32\fR
697: d1 /2 \fBrcll\fR \fIrm32\fR
698: d3 /2 \fBrcll\fR \fIcl,rm32\fR
699: c1 /2 \fBrcll\fR \fIimm8,rm32\fR
700: .sp \n(pDu
701: \fBrcr\fR Rotate carry right
702: d0 /3 \fBrcrb\fR \fIcon1,rm8\fR
703: d0 /3 \fBrcrb\fR \fIrm8\fR
704: d2 /3 \fBrcrb\fR \fIcl,rm8\fR
705: c0 /3 \fBrcrb\fR \fIimm8,rm8\fR
706: d1 /3 \fBrcrw\fR \fIcon1,rm16\fR
707: d1 /3 \fBrcrw\fR \fIrm16\fR
708: d3 /3 \fBrcrw\fR \fIcl,rm16\fR
709: c1 /3 \fBrcrw\fR \fIimm8,rm16\fR
710: d1 /3 \fBrcrl\fR \fIcon1,rm32\fR
711: d1 /3 \fBrcrl\fR \fIrm32\fR
712: d3 /3 \fBrcrl\fR \fIcl,rm32\fR
713: c1 /3 \fBrcrl\fR \fIimm8,rm32\fR
714: .sp \n(pDu
715: f3 \fBrep\fR rep following instruction CX times
716: f3 \fBrepe\fR repe following instruction CX times or eq
717: f2 \fBrepne\fR repne following instruction CX times or ne
718: f2 \fBrepnz\fR alternate name for repnz
719: f3 \fBrepz\fR alternate name for repe
720: c3 \fBret\fR Return
721: c2 \fBret\fR \fIimm16\fR Return pop imm16 bytes of parms
722: .sp \n(pDu
723: \fBrol\fR Rotate left
724: d0 /0 \fBrolb\fR \fIcon1,rm8\fR
725: d0 /0 \fBrolb\fR \fIrm8\fR
726: d2 /0 \fBrolb\fR \fIcl,rm8\fR
727: c0 /0 \fBrolb\fR \fIimm8,rm8\fR
728: d1 /0 \fBrolw\fR \fIcon1,rm16\fR
729: d1 /0 \fBrolw\fR \fIrm16\fR
730: d3 /0 \fBrolw\fR \fIcl,rm16\fR
731: c1 /0 \fBrolw\fR \fIimm8,rm16\fR
732: d1 /0 \fBroll\fR \fIcon1,rm32\fR
733: d1 /0 \fBroll\fR \fIrm32\fR
734: d3 /0 \fBroll\fR \fIcl,rm32\fR
735: c1 /0 \fBroll\fR \fIimm8,rm32\fR
736: .sp \n(pDu
737: \fBror\fR Rotate right
738: d0 /1 \fBrorb\fR \fIcon1,rm8\fR
739: d0 /1 \fBrorb\fR \fIrm8\fR
740: d2 /1 \fBrorb\fR \fIcl,rm8\fR
741: c0 /1 \fBrorb\fR \fIimm8,rm8\fR
742: d1 /1 \fBrorw\fR \fIcon1,rm16\fR
743: d1 /1 \fBrorw\fR \fIrm16\fR
744: d3 /1 \fBrorw\fR \fIcl,rm16\fR
745: c1 /1 \fBrorw\fR \fIimm8,rm16\fR
746: d1 /1 \fBrorl\fR \fIcon1,rm32\fR
747: d1 /1 \fBrorl\fR \fIrm32\fR
748: d3 /1 \fBrorl\fR \fIcl,rm32\fR
749: c1 /1 \fBrorl\fR \fIimm8,rm32\fR
750: .sp \n(pDu
751: 9e \fBsahf\fR Store AH into flags
752: .sp \n(pDu
753: \fBsal\fR Shift arithmetic left
754: d0 /4 \fBsalb\fR \fIcon1,rm8\fR
755: d0 /4 \fBsalb\fR \fIrm8\fR
756: d2 /4 \fBsalb\fR \fIcl,rm8\fR
757: c0 /4 \fBsalb\fR \fIimm8,rm8\fR
758: d1 /4 \fBsalw\fR \fIcon1,rm16\fR
759: d1 /4 \fBsalw\fR \fIrm16\fR
760: d3 /4 \fBsalw\fR \fIcl,rm16\fR
761: c1 /4 \fBsalw\fR \fIimm8,rm16\fR
762: d1 /4 \fBsall\fR \fIcon1,rm32\fR
763: d1 /4 \fBsall\fR \fIrm32\fR
764: d3 /4 \fBsall\fR \fIcl,rm32\fR
765: c1 /4 \fBsall\fR \fIimm8,rm32\fR
766: .sp \n(pDu
767: \fBsar\fR Shift arithmetic right
768: d0 /7 \fBsarb\fR \fIcon1,rm8\fR
769: d0 /7 \fBsarb\fR \fIrm8\fR
770: d2 /7 \fBsarb\fR \fIcl,rm8\fR
771: c0 /7 \fBsarb\fR \fIimm8,rm8\fR
772: d1 /7 \fBsarw\fR \fIcon1,rm16\fR
773: d1 /7 \fBsarw\fR \fIrm16\fR
774: d3 /7 \fBsarw\fR \fIcl,rm16\fR
775: c1 /7 \fBsarw\fR \fIimm8,rm16\fR
776: d1 /7 \fBsarl\fR \fIcon1,rm32\fR
777: d1 /7 \fBsarl\fR \fIrm32\fR
778: d3 /7 \fBsarl\fR \fIcl,rm32\fR
779: c1 /7 \fBsarl\fR \fIimm8,rm32\fR
780: .sp \n(pDu
781: \fBsbb\fR Subtract with borrow
782: 83 /3 \fBsbbl\fR \fIimm8s,rm32\fR
783: 83 /3 \fBsbbw\fR \fIimm8s,rm16\fR
784: 1c \fBsbbb\fR \fIimm8,al\fR
785: 1d \fBsbbw\fR \fIimm16,ax\fR
786: 1d \fBsbbl\fR \fIimm32,eax\fR
787: 1d \fBsbbl\fR \fIimm32\fR
788: 80 /3 \fBsbbb\fR \fIimm8,rm8\fR
789: 81 /3 \fBsbbw\fR \fIimm16,rm16\fR
790: 81 /3 \fBsbbl\fR \fIimm32,rm32\fR
791: 1a /r \fBsbbb\fR \fIrm8,r8\fR
792: 1b /r \fBsbbw\fR \fIrm16,r16\fR
793: 1b /r \fBsbbl\fR \fIrm32,r32\fR
794: 18 /r \fBsbbb\fR \fIr8,rm8\fR
795: 19 /r \fBsbbw\fR \fIr16,rm16\fR
796: 19 /r \fBsbbl\fR \fIr32,rm32\fR
797: .sp \n(pDu
798: ae \fBscasb\fR Compare string bytes
799: af \fBscasl\fR Compare string longs
800: af \fBscasw\fR Compare string words
801:
802: 0F 97 \fBseta\fR \fIrm8\fR Set byte if above
803: 0F 93 \fBsetae\fR \fIrm8\fR Set byte if above or equal
804: 0F 92 \fBsetb\fR \fIrm8\fR Set byte if below
805: 0F 96 \fBsetbe\fR \fIrm8\fR Set byte if below or equal
806: 0F 92 \fBsetc\fR \fIrm8\fR Set byte if carry
807: 0F 94 \fBsete\fR \fIrm8\fR Set byte if equal
808: 0F 9f \fBsetg\fR \fIrm8\fR Set byte if greater
809: 0F 9d \fBsetge\fR \fIrm8\fR Set byte if greater or equal
810: 0F 9c \fBsetl\fR \fIrm8\fR Set byte if less
811: 0F 9e \fBsetle\fR \fIrm8\fR Set byte if less or equal
812: 0F 96 \fBsetna\fR \fIrm8\fR Set byte if not above
813: 0F 92 \fBsetnae\fR \fIrm8\fR Set byte if not above or equal
814: 0F 93 \fBsetnb\fR \fIrm8\fR Set byte if not below
815: 0F 97 \fBsetnbe\fR \fIrm8\fR Set byte if not below or equal
816: 0F 93 \fBsetnc\fR \fIrm8\fR Set byte if no carry
817: 0F 95 \fBsetne\fR \fIrm8\fR Set byte if not equal
818: 0F 9e \fBsetng\fR \fIrm8\fR Set byte if not greater
819: 0F 9c \fBsetnge\fR \fIrm8\fR Set byte if not greater or equal
820: 0F 9d \fBsetnl\fR \fIrm8\fR Set byte if not less
821: 0F 9f \fBsetnle\fR \fIrm8\fR Set byte if not less or equal
822: 0F 91 \fBsetno\fR \fIrm8\fR Set byte if not overflow
823: 0F 9b \fBsetnp\fR \fIrm8\fR Set byte if not parity
824: 0F 99 \fBsetns\fR \fIrm8\fR Set byte if not sign
825: 0F 95 \fBsetnz\fR \fIrm8\fR Set byte if not zero
826: 0F 90 \fBseto\fR \fIrm8\fR Set byte if overflow
827: 0F 9a \fBsetp\fR \fIrm8\fR Set byte if parity
828: 0F 9a \fBsetpe\fR \fIrm8\fR Set byte if parity even
829: 0F 9b \fBsetpo\fR \fIrm8\fR Set byte if parity odd
830: 0F 98 \fBsets\fR \fIrm8\fR Set byte if sign
831: 0F 94 \fBsetz\fR \fIrm8\fR Set byte if zero
832: 0F 94 \fBsetz\fR \fIrm8\fR Set byte if zero
833:
834: 0F 01 /0 \fBsgdt\fR \fImem32\fR Store gdtr
835: .sp \n(pDu
836: \fBshl\fR Shift arithmetic left
837: d0 /4 \fBshlb\fR \fIcon1,rm8\fR
838: d0 /4 \fBshlb\fR \fIrm8\fR
839: d2 /4 \fBshlb\fR \fIcl,rm8\fR
840: c0 /4 \fBshlb\fR \fIimm8,rm8\fR
841: d1 /4 \fBshlw\fR \fIcon1,rm16\fR
842: d1 /4 \fBshlw\fR \fIrm16\fR
843: d3 /4 \fBshlw\fR \fIcl,rm16\fR
844: c1 /4 \fBshlw\fR \fIimm8,rm16\fR
845: d1 /4 \fBshll\fR \fIcon1,rm32\fR
846: d1 /4 \fBshll\fR \fIrm32\fR
847: d3 /4 \fBshll\fR \fIcl,rm32\fR
848: c1 /4 \fBshll\fR \fIimm8,rm32\fR
849: .sp \n(pDu
850: \fBshld\fR Shift double precision left
851: 0F a4 \fBshldw\fR \fIimm8,r16,rm16\fR
852: 0F a4 \fBshldl\fR \fIimm8,r32,rm32\fR
853: 0F a5 \fBshldw\fR \fIcl,r16,rm16\fR
854: 0F a5 \fBshldl\fR \fIcl,r32,rm32\fR
855: .sp \n(pDu
856: \fBshr\fR Shift right
857: d0 /5 \fBshrb\fR \fIcon1,rm8\fR
858: d0 /5 \fBshrb\fR \fIrm8\fR
859: d2 /5 \fBshrb\fR \fIcl,rm8\fR
860: c0 /5 \fBshrb\fR \fIimm8,rm8\fR
861: d1 /5 \fBshrw\fR \fIcon1,rm16\fR
862: d1 /5 \fBshrw\fR \fIrm16\fR
863: d3 /5 \fBshrw\fR \fIcl,rm16\fR
864: c1 /5 \fBshrw\fR \fIimm8,rm16\fR
865: d1 /5 \fBshrl\fR \fIcon1,rm32\fR
866: d1 /5 \fBshrl\fR \fIrm32\fR
867: d3 /5 \fBshrl\fR \fIcl,rm32\fR
868: c1 /5 \fBshrl\fR \fIimm8,rm32\fR
869: .sp \n(pDu
870: \fBshrd\fR Shift double precision right
871: 0F ac \fBshrdw\fR \fIimm8,r16,rm16\fR
872: 0F ac \fBshrdl\fR \fIimm8,r32,rm32\fR
873: 0F ad \fBshrdw\fR \fIcl,r16,rm16\fR
874: 0F ad \fBshrdl\fR \fIcl,r32,rm32\fR
875: 0F ad \fBshrdw\fR \fIr16,rm16\fR
876: 0F ad \fBshrdl\fR \fIr32,rm32\fR
877: .sp \n(pDu
878: 0F 01 /1 \fBsidt\fR \fImem32\fR Store idtr
879: 0F 00 /0 \fBsldt\fR \fIrm16\fR Store ldtr to EA word
880: 0F 01 /4 \fBsmsw\fR \fIrm16\fR Store machine status to EA word
881: f9 \fBstc\fR Set carry flag
882: fd \fBstd\fR Clear direction flag
883: fb \fBsti\fR Set interrupt flag
884: aa \fBstosb\fR Store string byte
885: ab \fBstosl\fR Store string long
886: ab \fBstosw\fR Store string word
887: 0F 00 /1 \fBstr\fR Store task register
888: .sp \n(pDu
889: \fBsub\fR Subtract
890: 83 /5 \fBsubl\fR \fIimm8s,rm32\fR
891: 83 /5 \fBsubw\fR \fIimm8s,rm16\fR
892: 2c \fBsubb\fR \fIimm8,al\fR
893: 2d \fBsubw\fR \fIimm16,ax\fR
894: 2d \fBsubl\fR \fIimm32,eax\fR
895: 2d \fBsubl\fR \fIimm32\fR
896: 80 /5 \fBsubb\fR \fIimm8,rm8\fR
897: 81 /5 \fBsubw\fR \fIimm16,rm16\fR
898: 81 /5 \fBsubl\fR \fIimm32,rm32\fR
899: 2a /r \fBsubb\fR \fIrm8,r8\fR
900: 2b /r \fBsubw\fR \fIrm16,r16\fR
901: 2b /r \fBsubl\fR \fIrm32,r32\fR
902: 28 /r \fBsubb\fR \fIr8,rm8\fR
903: 29 /r \fBsubw\fR \fIr16,rm16\fR
904: 29 /r \fBsubl\fR \fIr32,rm32\fR
905: .sp \n(pDu
906: \fBtest\fR Logical compare
907: a8 \fBtestb\fR \fIimm8,al\fR
908: a9 \fBtestw\fR \fIimm16,ax\fR
909: a9 \fBtestl\fR \fIimm32,eax\fR
910: a9 \fBtestl\fR \fIimm32\fR
911: f6 /0 \fBtestb\fR \fIimm8,rm8\fR
912: f7 /0 \fBtestw\fR \fIimm16,rm16\fR
913: f7 /0 \fBtestl\fR \fIimm32,rm32\fR
914: 84 /r \fBtestb\fR \fIr8,rm8\fR
915: 85 /r \fBtestw\fR \fIr16,rm16\fR
916: 85 /r \fBtestl\fR \fIr32,rm32\fR
917: .sp \n(pDu
918: 0F 00 /4 \fBverr\fR \fIrm16\fR Verify segment for read
919: 0F 00 /5 \fBverw\fR \fIrm16\fR Verify segment for write
920: 9b \fBwait\fR Wait for coprocessor
921: .sp \n(pDu
922: \fBxchg\fR Exchange register
923: 90 +r \fBxchgw\fR \fIr16,ax\fR
924: 90 +r \fBxchgw\fR \fIax,r16\fR
925: 90 +r \fBxchgl\fR \fIr32,eax\fR
926: 90 +r \fBxchgl\fR \fIr32\fR
927: 90 +r \fBxchgl\fR \fIeax,r32\fR
928: 86 /r \fBxchgb\fR \fIrm8,r8\fR
929: 87 /r \fBxchgw\fR \fIrm16,r16\fR
930: 87 /r \fBxchgl\fR \fIrm32,r32\fR
931: 86 /r \fBxchgb\fR \fIr8,rm8\fR
932: 87 /r \fBxchgw\fR \fIr16,rm16\fR
933: 87 /r \fBxchgl\fR \fIr32,rm32\fR
934: .sp \n(pDu
935: d7 \fBxlat\fR Table lookup translation
936: d7 \fBxlatb\fR Table lookup translation
937: .sp \n(pDu
938: \fBxor\fR Logical exclusive OR
939: 83 /6 \fBxorl\fR \fIimm8s,rm32\fR
940: 83 /6 \fBxorw\fR \fIimm8s,rm16\fR
941: 34 \fBxorb\fR \fIimm8,al\fR
942: 35 \fBxorw\fR \fIimm16,ax\fR
943: 35 \fBxorl\fR \fIimm32,eax\fR
944: 35 \fBxorl\fR \fIimm32\fR
945: 80 /6 \fBxorb\fR \fIimm8,rm8\fR
946: 81 /6 \fBxorw\fR \fIimm16,rm16\fR
947: 81 /6 \fBxorl\fR \fIimm32,rm32\fR
948: 32 /r \fBxorb\fR \fIrm8,r8\fR
949: 33 /r \fBxorw\fR \fIrm16,r16\fR
950: 33 /r \fBxorl\fR \fIrm32,r32\fR
951: 30 /r \fBxorb\fR \fIr8,rm8\fR
952: 31 /r \fBxorw\fR \fIr16,rm16\fR
953: 31 /r \fBxorl\fR \fIr32,rm32\fR
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