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1.1 ! root 1: /* ! 2: * h/i386/mch.h ! 3: * Machine specific header for the i386 compiler. ! 4: * Typedefs, register names and macros for all compiler phases. ! 5: * This one builds a debug (!TINY) i386 COHERENT compiler with disk tempfiles and NDP fp. ! 6: */ ! 7: ! 8: #define DATE "10/1/92" /* Date */ ! 9: #define VERSMWC "V4.0.A" /* MWC version number */ ! 10: #define VERSINT "X324" /* Intel version number */ ! 11: ! 12: #define EATDOL 0 /* Eat '$' in identifiers? */ ! 13: #define APPENDBAR 0 /* Append '_' to identifiers? */ ! 14: #define IEEE 1 /* IEEE format? */ ! 15: #define DECVAX 0 /* DECVAX format? */ ! 16: #define NATIVEFP 0 /* Host fp == target fp? */ ! 17: #define MCFFP 0 /* Motorola fast floating point? */ ! 18: #define TINY 0 /* No code gen debug info? */ ! 19: #ifndef YATC ! 20: #define YATC 0 /* Not code table compile */ ! 21: #endif ! 22: #define SIZEOF_LARGE 0 /* sizeof_t == ival_t */ ! 23: #define SPLIT_CC1 0 /* CC1A-CC1B? */ ! 24: #define AS_FORMAT 1 /* Coherent/Rainbow .s format? */ ! 25: #define INTEL 0 /* Intel copyright? */ ! 26: #define OMF286 0 /* 286 object format? */ ! 27: #define TEMPBUF 0 /* Memory tempfile buffers? */ ! 28: ! 29: #define NDP 1 /* 8087? */ ! 30: #define EMUFIXUPS 0 /* M: 8087 emulation fixups? */ ! 31: ! 32: /* ! 33: * Types. ! 34: * Cf. common/i386/tyname.c. ! 35: */ ! 36: #define S8 0 /* Signed byte */ ! 37: #define U8 1 /* Unsigned byte */ ! 38: #define S16 2 /* Signed word */ ! 39: #define U16 3 /* Unsigned word */ ! 40: #define S32 4 /* Signed long */ ! 41: #define U32 5 /* Unsigned long */ ! 42: #define F32 6 /* Short floating point */ ! 43: #define F64 7 /* Long floating point */ ! 44: #define BLK 8 /* Block of bytes */ ! 45: #define FLD8 9 /* Field, byte wide */ ! 46: #define FLD16 10 /* Field, word wide */ ! 47: #define FLD32 11 /* Field, dword wide */ ! 48: #define PTR 12 /* Pointer */ ! 49: #define PTB 13 /* Pointer to BLK */ ! 50: ! 51: #define TRUTH S32 /* Type used for truth values */ ! 52: #define OFFS PTR /* Offset LEAF type */ ! 53: #define IVAL_T S32 /* Type for ival_t con */ ! 54: #define LVAL_T S32 /* Type for lval_t con */ ! 55: #define DVAL_T F64 /* Type for dval_t con */ ! 56: #define I_FMT "%ld" /* printf format for ival_t con */ ! 57: #define I_FMTX "%lx" /* printf format for ival_t con */ ! 58: #define NBPBYTE 8 /* # of bits in a "byte" */ ! 59: ! 60: /* ! 61: * Flag bit type for each machine type. ! 62: */ ! 63: #define FS8 0x0001 ! 64: #define FU8 0x0002 ! 65: #define FS16 0x0004 ! 66: #define FU16 0x0008 ! 67: #define FS32 0x0010 ! 68: #define FU32 0x0020 ! 69: #define FF32 0x0040 ! 70: #define FF64 0x0080 ! 71: #define FBLK 0x0100 ! 72: #define FFLD8 0x0200 ! 73: #define FFLD16 0x0400 ! 74: #define FFLD32 0x0800 ! 75: #define FPTR 0x1000 ! 76: #define FPTB 0x2000 ! 77: ! 78: /* ! 79: * Allocation types. ! 80: */ ! 81: #ifdef vax ! 82: typedef int ival_t; /* 32 bits */ ! 83: typedef int lval_t; /* 32 bits */ ! 84: typedef int sizeof_t; /* sizeof constants */ ! 85: #else ! 86: typedef long ival_t; /* 32 bit ints */ ! 87: typedef long lval_t; /* 32 bit longs */ ! 88: typedef long sizeof_t; /* 32 bit sizeof constants */ ! 89: #endif ! 90: typedef char dval_t[8]; /* doubles */ ! 91: ! 92: /* ! 93: * Types used in several phases. ! 94: */ ! 95: typedef int PREGSET; ! 96: typedef unsigned long ADDRESS; ! 97: typedef long SIGNEDADDRESS; ! 98: ! 99: /* ! 100: * Limits. ! 101: */ ! 102: #define MAXIV 0x7FFFFFFFL /* Max integer */ ! 103: #define MAXUV 0xFFFFFFFFL /* Max unsigned integer */ ! 104: #define MAXUCE 255 /* Max unsigned char enumeration */ ! 105: #define UIMASK 0x00000000L /* Unsigned int check mask */ ! 106: #define SIMASK 0x80000000L /* Signed int check mask */ ! 107: #define SLMASK 0x80000000L /* Signed long check mask */ ! 108: #define ASMASK 0xFFFFFFFFL /* Address space mask */ ! 109: #define MAXMEMB MAXIV /* Max struct/union member offset */ ! 110: #define MAXESIZE MAXUV /* Max struct/union/array size */ ! 111: ! 112: /* ! 113: * Registers. ! 114: * This list includes the machine's actual registers, ! 115: * registers that are given names for the benefit of the code output routines, ! 116: * and the pseudo registers used by the code generator. ! 117: * Cf. common/i386/regnam.c, n1/i386/gen1.c, n1/i386/table1.c. ! 118: */ ! 119: /* 32-bit general registers. */ ! 120: #define EAX 0 ! 121: #define EDX 1 ! 122: #define EBX 2 ! 123: #define ECX 3 ! 124: #define ESI 4 ! 125: #define EDI 5 ! 126: #define ESP 6 ! 127: #define EBP 7 ! 128: ! 129: /* Quad-word register for multiplication, division, floating point. */ ! 130: #define EDXEAX 8 ! 131: ! 132: /* 16-bit i8086 registers. */ ! 133: #define AX 9 ! 134: #define DX 10 ! 135: #define BX 11 ! 136: #define CX 12 ! 137: #define SI 13 ! 138: #define DI 14 ! 139: #define SP 15 ! 140: #define BP 16 ! 141: ! 142: /* Eight-bit parts of i8086 registers. */ ! 143: #define AL 17 ! 144: #define BL 18 ! 145: #define CL 19 ! 146: #define DL 20 ! 147: #define AH 21 ! 148: #define BH 22 ! 149: #define CH 23 ! 150: #define DH 24 ! 151: ! 152: /* Floating point register (NDP stacktop %st0), used by NDP version only. */ ! 153: #define FPAC 25 ! 154: ! 155: /* Pseudoregisters. */ ! 156: #define NONE 26 ! 157: #define ANYR 27 ! 158: #define ANYL 28 ! 159: #define PAIR 29 ! 160: #define TEMP 30 ! 161: #define LOTEMP 31 ! 162: #define HITEMP 32 ! 163: ! 164: #define FRREG EAX /* First real reg */ ! 165: #define NFBREG 7 /* Number of last flag bit reg */ ! 166: #define NRREG 25 /* Number of real regs */ ! 167: #define NREG 31 /* Number of last reg */ ! 168: ! 169: /* Flag bits, same order as register numbers above. */ ! 170: #define BEAX 0x0001 ! 171: #define BEDX 0x0002 ! 172: #define BEBX 0x0004 ! 173: #define BECX 0x0008 ! 174: #define BESI 0x0010 ! 175: #define BEDI 0x0020 ! 176: #define BESP 0x0040 ! 177: #define BEBP 0x0080 ! 178: #define BFPAC 0x0100 ! 179: ! 180: /* ! 181: * Machine registers. ! 182: * The processor uses these codes in the REGM field of an instruction. ! 183: * This makes it easier to get the register code from an AFIELD ! 184: * and to find the indexing mode associated with a register. ! 185: * Unless Intel changes the chip, do not change the values here. ! 186: */ ! 187: #define MEAX 0 ! 188: #define MECX 1 ! 189: #define MEDX 2 ! 190: #define MEBX 3 ! 191: #define MESP 4 ! 192: #define MEBP 5 ! 193: #define MESI 6 ! 194: #define MEDI 7 ! 195: ! 196: #define NMREG 8 ! 197: ! 198: /* ! 199: * Definitions for the "a_mode" field of an AFIELD object (cc1, cc2). ! 200: * Some bits are used only by the peephole optimizer in the "regstate" table. ! 201: * The indexing mode bits are packed efficiently but not very intuitively. ! 202: */ ! 203: #define A_NONE 0 /* General "none" value */ ! 204: #define A_REGM 0x0007 /* Register code, etc. */ ! 205: #define A_IREG 0x0038 /* Scaled index register code */ ! 206: #define A_ISS 0x00C0 /* Scale factor, [0123] for [1248] */ ! 207: #define A_AMOD 0x0F00 /* Address mode */ ! 208: #define A_X 0x0800 /* Flag for indexed address modes */ ! 209: #define A_FLAGS 0xF000 /* Flag bit mask */ ! 210: #define A_EA 0x1000 /* Flag for peephole; effective address */ ! 211: #define A_OFFS 0x2000 /* Flag for getfield; offset present */ ! 212: #define A_LID 0x4000 /* Flag for getfield; local id present */ ! 213: #define A_GID 0x8000 /* Flag for getfield; global id present */ ! 214: ! 215: #define NOBASE -1 /* No SIB base present */ ! 216: #define SIB(m) ((m) & 0xFF) /* Extract SIB */ ! 217: #define IREG(m) (((m) & A_IREG) >> 3) /* Extract index reg */ ! 218: #define SCALE(m) (((m) & A_ISS) >> 6) /* Extract scale factor */ ! 219: ! 220: /* A_AMOD values. */ ! 221: #define A_BR (1<<8) /* Byte register */ ! 222: #define A_WR (2<<8) /* Word register */ ! 223: #define A_DR (3<<8) /* Dword register */ ! 224: #define A_IMM (4<<8) /* Immediate */ ! 225: #define A_DIR (5<<8) /* Direct */ ! 226: #define A_XB (A_X|(6<<8)) /* Indexed using base register only */ ! 227: #define A_XSIB (A_X|(7<<8)) /* Indexed using SIB */ ! 228: ! 229: #define A_REAX (A_DR|MEAX) /* eax */ ! 230: #define A_RECX (A_DR|MECX) /* ecx */ ! 231: #define A_REDX (A_DR|MEDX) /* edx */ ! 232: #define A_REBX (A_DR|MEBX) /* ebx */ ! 233: #define A_RESP (A_DR|MESP) /* esp */ ! 234: #define A_REBP (A_DR|MEBP) /* ebp */ ! 235: #define A_RESI (A_DR|MESI) /* esi */ ! 236: #define A_REDI (A_DR|MEDI) /* edi */ ! 237: ! 238: #define A_RAX (A_WR|MEAX) /* ax */ ! 239: #define A_RCX (A_WR|MECX) /* cx */ ! 240: #define A_RDX (A_WR|MEDX) /* dx */ ! 241: #define A_RBX (A_WR|MEBX) /* bx */ ! 242: #define A_RSP (A_WR|MESP) /* sp */ ! 243: #define A_RBP (A_WR|MEBP) /* bp */ ! 244: #define A_RSI (A_WR|MESI) /* si */ ! 245: #define A_RDI (A_WR|MEDI) /* di */ ! 246: ! 247: #define A_RAL (A_BR|MEAX) /* al */ ! 248: #define A_RCL (A_BR|MECX) /* cl */ ! 249: #define A_RDL (A_BR|MEDX) /* dl */ ! 250: #define A_RBL (A_BR|MEBX) /* bl */ ! 251: #define A_RAH (A_BR|MEAX|4) /* ah */ ! 252: #define A_RCH (A_BR|MECX|4) /* ch */ ! 253: #define A_RDH (A_BR|MEDX|4) /* dh */ ! 254: #define A_RBH (A_BR|MEBX|4) /* bh */ ! 255: ! 256: #define A_XEAX (A_XB|MEAX) /* [eax] */ ! 257: #define A_XECX (A_XB|MECX) /* [ecx] */ ! 258: #define A_XEDX (A_XB|MEDX) /* [edx] */ ! 259: #define A_XEBX (A_XB|MEBX) /* [ebx] */ ! 260: #define A_XEBP (A_XB|MEBP) /* [ebp] */ ! 261: #define A_XESI (A_XB|MESI) /* [esi] */ ! 262: #define A_XEDI (A_XB|MEDI) /* [edi] */ ! 263: ! 264: /* end of h/i386/mch.h */
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