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1.1 root 1: //////////
2: / n1/i386/tables/adiv.t
3: //////////
4:
5: /////////
6: /
7: / Assigned divide (/=).
8: / Use unsigned divide if either left or right operand is unsigned.
9: /
10: /////////
11:
12: ADIV:
13:
14: / Unsigned integer by unsigned.
15: / The result word or byte does not have to be sign- or zero-extended
16: / in value context, the result is already correct.
17: % PEFFECT|PVALUE
18: LONG EDXEAX * * EAX
19: ADR|LV UINT
20: ADR LONG
21: / Signed long by unsigned.
22: % PEFFECT|PVALUE
23: LONG EDXEAX * * EAX
24: ADR|LV FS32
25: ADR FU32
26: [TL ZMOVSX] [REGNO EAX], [AL]
27: [ZSUB] [REGNO EDX], [REGNO EDX]
28: [ZDIV] [AR]
29: [TL ZMOV] [AL], [TL REGNO EAX]
30:
31: / Signed word or byte by unsigned.
32: / The result must be sign- or zero-extended in value context.
33: % PEFFECT|PVALUE
34: LONG EDXEAX * * EAX
35: ADR|LV FS16|FS8
36: ADR FU32
37: [TL ZMOVSX] [REGNO EAX], [AL]
38: [ZSUB] [REGNO EDX], [REGNO EDX]
39: [ZDIV] [AR]
40: [TL ZMOV] [AL], [TL REGNO EAX]
41: [IFV] [TL ZMOVSX] [REGNO EAX], [TL REGNO EAX]
42:
43: / Signed integer by signed.
44: / The result word or byte does not have to be sign- or zero-extended
45: / in value context, the result is already correct.
46: % PEFFECT|PVALUE
47: LONG EDXEAX * * EAX
48: ADR|LV SINT
49: ADR FS32
50: [TL ZMOVSX] [REGNO EAX], [AL]
51: [ZCDQ]
52: [ZIDIV] [AR]
53: [TL ZMOV] [AL], [TL REGNO EAX]
54:
55: //////////
56: / Fields.
57: / The right hand operand of the field is not preshifted
58: / like it is for add, subtract and the increment/decrement ops.
59: //////////
60:
61: / Field.
62: % PEFFECT|PVALUE
63: LONG EDXEAX * * EAX
64: ADR|LV FLD
65: ADR LONG
66: [TL ZMOVZX] [REGNO EAX],[AL] / fetch
67: [ZAND] [REGNO EAX],[EMASK] / extract
68: [ZSUB] [REGNO EDX],[REGNO EDX] / widen
69: [ZDIV] [AR] / divide
70: [ZAND] [REGNO EAX],[EMASK] / mask
71: [TL ZAND] [AL],[TL CMASK] / clear
72: [TL ZOR] [AL],[TL REGNO EAX] / store
73:
74: //////////
75: / Floating point.
76: //////////
77:
78: / IEEE or DECVAX software floating point.
79: / Double /= double.
80: % PEFFECT|PVALUE|P_SRT|PDECVAX|PIEEE
81: FF64 EDXEAX * EDXEAX TEMP
82: ADR|LV FF64
83: TREG FF64
84: [ZPUSH] [HI AL]
85: [ZPUSH] [LO AL]
86: [ZCALL] [GID _ddiv]
87: [ZADD] [REGNO ESP],[CONST 8]
88: [ZMOV] [HI AL],[HI R]
89: [ZMOV] [LO AL],[LO R]
90:
91: / Float /= double.
92: % PEFFECT|PVALUE|P_SRT|PDECVAX|PIEEE
93: FF64 EDXEAX * EDXEAX TEMP
94: ADR|LV FF32
95: TREG FF64
96: [ZPUSH] [AL]
97: [ZCALL] [GID _fdiv]
98: [ZADD] [REGNO ESP],[CONST 4]
99: [ZCALL] [GID _fdcvt]
100: [ZMOV] [AL], [LO R]
101: [IFV] [ZCALL] [GID _dfcvt]
102:
103: / Hardware coprocessor (NDP) floating point.
104: % PEFFECT|PVALUE|PNDP
105: FLOAT FPAC * FPAC FPAC
106: ADR|LV FLOAT
107: TREG FF64
108: [TL ZFRDIVD] [AL]
109: [IFV] [TL ZFSTD] [AL]
110: [IFE] [TL ZFSTPD] [AL]
111:
112: //////////
113: / end of n1/i386/tables/adiv.t
114: //////////
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