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1.1 root 1: /////////
2: /
3: / Assigned and. If field, the right tree has been modified to have the
4: / clearing mask ored into it. This means that an and may be aimed at the
5: / word or byte containing the field and all bits not actually in the field
6: / will be unchanged.
7: /
8: /////////
9:
10: AAND:
11: % PEFFECT|PRVALUE|PREL
12: WORD ANYR * * TEMP
13: RREG|MMX WORD
14: EASY|MMX WORD
15: % PEFFECT|PRVALUE|PREL
16: WORD ANYR * * TEMP
17: ADR|LV WORD
18: IMM|MMX WORD
19: [ZAND] [AL],[AR]
20: [IFV] [ZMOV] [R],[AL]
21: [IFR] [REL0] [LAB]
22:
23: % PEFFECT|PRVALUE|PREL
24: WORD AX * * AX
25: ADR|LV FS8
26: IMM|MMX WORD
27: [ZANDB] [AL],[AR]
28: [IFV] [ZMOVB] [LO R],[AL]
29: [IFV] [ZCBW]
30: [IFR] [REL0] [LAB]
31:
32: % PEFFECT|PRVALUE|PREL
33: WORD AX * * AX
34: ADR|LV FU8
35: IMM|MMX WORD
36: [ZANDB] [AL],[AR]
37: [IFV] [ZMOVB] [LO R],[AL]
38: [IFV] [ZSUBB] [HI R],[HI R]
39: [IFR] [REL0] [LAB]
40:
41: % PEFFECT|PRVALUE|PREL|P_SRT
42: WORD ANYR * ANYR TEMP
43: ADR|LV WORD
44: TREG WORD
45: [ZAND] [AL],[R]
46: [IFV] [ZMOV] [R],[AL]
47: [IFR] [REL0] [LAB]
48:
49: % PEFFECT|PRVALUE|PREL|P_SRT
50: WORD AX * AX AX
51: ADR|LV FS8
52: TREG WORD
53: [ZANDB] [AL],[LO R]
54: [IFV] [ZMOVB] [LO R],[AL]
55: [IFV] [ZCBW]
56: [IFR] [REL0] [LAB]
57:
58: % PEFFECT|PRVALUE|PREL|P_SRT
59: WORD AX * AX AX
60: ADR|LV FU8
61: TREG WORD
62: [ZANDB] [AL],[LO R]
63: [IFV] [ZMOVB] [LO R],[AL]
64: [IFV] [ZSUBB] [HI R],[HI R]
65: [IFR] [REL0] [LAB]
66:
67: % PEFFECT|PRVALUE|PLT|PGE
68: LONG DXAX * * DXAX
69: ADR|LV LONG
70: LHC|MMX LONG
71: [ZMOV] [LO AL],[LO AR]
72: [ZAND] [HI AL],[HI AR]
73: [IFV] [ZMOV] [LO R],[LO AL]
74: [IFV] [ZMOV] [HI R],[HI AL]
75: [IFR] [REL1] [LAB]
76:
77: % PEFFECT|PRVALUE
78: LONG DXAX * * DXAX
79: ADR|LV LONG
80: LHS|MMX LONG
81: [ZAND] [HI AL],[HI AR]
82: [IFV] [ZMOV] [LO R],[LO AL]
83: [IFV] [ZMOV] [HI R],[HI AL]
84:
85: % PEFFECT|PRVALUE
86: LONG DXAX * * DXAX
87: ADR|LV LONG
88: UHC|MMX LONG
89: [ZAND] [LO AL],[LO AR]
90: [ZMOV] [HI AL],[HI AR]
91: [IFV] [ZMOV] [LO R],[LO AL]
92: [IFV] [ZMOV] [HI R],[HI AL]
93:
94: % PEFFECT|PRVALUE
95: LONG DXAX * * DXAX
96: ADR|LV LONG
97: UHS|MMX LONG
98: [ZAND] [LO AL],[LO AR]
99: [IFV] [ZMOV] [LO R],[LO AL]
100: [IFV] [ZMOV] [HI R],[HI AL]
101:
102: % PEFFECT|PRVALUE|PLT|PGE
103: LONG DXAX * * DXAX
104: ADR|LV LONG
105: IMM|MMX LONG
106: [ZAND] [LO AL],[LO AR]
107: [ZAND] [HI AL],[HI AR]
108: [IFV] [ZMOV] [LO R],[LO AL]
109: [IFV] [ZMOV] [HI R],[HI AL]
110: [IFR] [REL1] [LAB]
111:
112: % PEFFECT|PRVALUE
113: LONG DXAX * DXAX DXAX
114: ADR|LV LONG
115: TREG LONG
116: [ZAND] [LO AL],[LO R]
117: [ZAND] [HI AL],[HI R]
118: [IFV] [ZMOV] [LO R],[LO AL]
119: [IFV] [ZMOV] [HI R],[HI AL]
120:
121: /////////
122: /
123: / Fields. Distinguish between signed and unsigned fields. If the value
124: / is needed the mask must be done for unsigned fields. The sign extend
125: / shifts don't need the mask, so it gets optimized out.
126: /
127: /////////
128:
129: % PEFFECT|PRVALUE
130: FS16 ANYR * * TEMP
131: ADR|LV FFLD16
132: DIR|IMM|MMX WORD
133: [ZAND] [AL],[AR]
134: [IFV] [ZMOV] [R],[AL]
135:
136: % PEFFECT|PRVALUE
137: UWORD ANYR * * TEMP
138: ADR|LV FFLD16
139: DIR|IMM|MMX WORD
140: [ZAND] [AL],[AR]
141: [IFV] [ZMOV] [R],[AL]
142: [IFV] [ZAND] [R],[LO EMASK]
143:
144: % PEFFECT|PRVALUE
145: FS16 AX * * TEMP
146: ADR|LV FFLD8
147: DIR|IMM|MMX WORD
148: [ZANDB] [AL],[AR]
149: [IFV] [ZMOVB] [LO R],[AL]
150:
151: % PEFFECT|PRVALUE
152: UWORD ANYR * * TEMP
153: ADR|LV FFLD8
154: DIR|IMM|MMX WORD
155: [ZANDB] [AL],[AR]
156: [IFV] [ZMOVB] [LO R],[AL]
157: [IFV] [ZAND] [R],[LO EMASK]
158:
159: % PEFFECT|PRVALUE|P_SRT
160: FS16 ANYR * ANYR TEMP
161: ADR|LV FFLD16
162: TREG WORD
163: [ZAND] [AL],[R]
164: [IFV] [ZMOV] [R],[AL]
165:
166: % PEFFECT|PRVALUE|P_SRT
167: UWORD ANYR * ANYR TEMP
168: ADR|LV FFLD16
169: TREG WORD
170: [ZAND] [AL],[R]
171: [IFV] [ZMOV] [R],[AL]
172: [IFV] [ZAND] [R],[LO EMASK]
173:
174: % PEFFECT|PRVALUE|P_SRT
175: FS16 AX * AX TEMP
176: ADR|LV FFLD8
177: TREG WORD
178: [ZANDB] [AL],[LO R]
179: [IFV] [ZMOVB] [LO R],[AL]
180:
181: % PEFFECT|PRVALUE|P_SRT
182: UWORD AX * AX TEMP
183: ADR|LV FFLD8
184: TREG WORD
185: [ZANDB] [AL],[LO R]
186: [IFV] [ZMOVB] [LO R],[AL]
187: [IFV] [ZAND] [R],[LO EMASK]
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