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1.1 root 1: /////////
2: /
3: / Addition.
4: / Check for +1 (inc) and +2 (inc, inc; thanks to Mac).
5: / Handle LARGE model addition of integers and pointers,
6: / which are OFFSET adjustments only.
7: /
8: /////////
9:
10: ADD:
11: % PEFFECT|PRVALUE|PSREL|P_SLT
12: WORD ANYR ANYR * TEMP
13: TREG WORD
14: 1|MMX *
15: % PLVALUE|P_SLT
16: WORD ANYL ANYL * TEMP
17: TREG WORD
18: 1|MMX *
19: [ZINC] [R]
20: [IFR] [REL0] [LAB]
21:
22: #ifndef ONLYSMALL
23: % PEFFECT|PRVALUE|P_SLT
24: LPTX ANYR ANYR * TEMP
25: TREG LPTX
26: 1|MMX *
27: % PLVALUE|P_SLT
28: LPTX ANYL ANYL * TEMP
29: TREG LPTX
30: 1|MMX *
31: [ZINC] [LO R]
32: #endif
33:
34: % PEFFECT|PRVALUE|PSREL|P_SLT
35: WORD ANYR ANYR * TEMP
36: TREG WORD
37: 2|MMX *
38: % PLVALUE|P_SLT
39: WORD ANYL ANYL * TEMP
40: TREG WORD
41: 2|MMX *
42: [ZINC] [R]
43: [ZINC] [R]
44: [IFR] [REL0] [LAB]
45:
46: #ifndef ONLYSMALL
47: % PEFFECT|PRVALUE|P_SLT
48: LPTX ANYR ANYR * TEMP
49: TREG LPTX
50: 2|MMX *
51: % PLVALUE|P_SLT
52: LPTX ANYL ANYL * TEMP
53: TREG LPTX
54: 2|MMX *
55: [ZINC] [LO R]
56: [ZINC] [LO R]
57: #endif
58:
59: % PEFFECT|PRVALUE|PSREL|P_SLT
60: WORD ANYR ANYR * TEMP
61: TREG WORD
62: ADR|IMM WORD
63: % PLVALUE|P_SLT
64: WORD ANYL ANYL * TEMP
65: TREG WORD
66: ADR|IMM WORD
67: [ZADD] [R],[AR]
68: [IFR] [REL0] [LAB]
69:
70: #ifndef ONLYSMALL
71: % PEFFECT|PRVALUE|P_SLT
72: LPTX ANYR ANYR * TEMP
73: TREG LPTX
74: ADR|IMM WORD
75: % PLVALUE|P_SLT
76: LPTX ANYL ANYL * TEMP
77: TREG LPTX
78: ADR|IMM WORD
79: [ZADD] [LO R],[AR]
80: #endif
81:
82: /////////
83: /
84: / Index like contexts.
85: / The hard tree is an integer and the
86: / result is a pointer. There are a lot of
87: / cases here, mainly to make sure the
88: / correct segment base gets moved over to
89: / the result.
90: /
91: /////////
92:
93: #ifndef ONLYSMALL
94: % PEFFECT|PRVALUE
95: LPTX DXAX AX * TEMP
96: TREG WORD
97: ICN|MMX LPTX
98: [ZADD] [LO R],[AR]
99: [ZSUB] [HI R],[HI R]
100:
101: % PLVALUE
102: LPTX ANYL LOTEMP AX TEMP
103: TREG WORD
104: ICN|MMX LPTX
105: [ZADD] [LO R],[AR]
106: [ZSUB] [REGNO AX],[REGNO AX]
107: [ZMOV] [HI R],[REGNO AX]
108:
109: % PEFFECT|PRVALUE
110: LPTX DXAX AX * TEMP
111: TREG WORD
112: LCN|MMX LPTX
113: [ZADD] [LO R],[LO AR]
114: [ZSUB] [HI R],[HI R]
115:
116: % PLVALUE
117: LPTX ANYL LOTEMP AX TEMP
118: TREG WORD
119: LCN|MMX LPTX
120: [ZADD] [LO R],[LO AR]
121: [ZMOV] [REGNO AX],[HI AR]
122: [ZMOV] [HI R],[REGNO AX]
123:
124: % PEFFECT|PRVALUE
125: LPTX DXAX AX * TEMP
126: TREG WORD
127: ACS|MMX LPTX
128: [ZADD] [LO R],[AR]
129: [ZMOV] [HI R],[REGNO CS]
130:
131: % PEFFECT|PRVALUE
132: LPTX DXAX AX * TEMP
133: TREG WORD
134: ADS|MMX LPTX
135: [ZADD] [LO R],[AR]
136: [ZMOV] [HI R],[REGNO DS]
137:
138: % PLVALUE
139: LPTX ANYL LOTEMP * TEMP
140: TREG WORD
141: ACS|MMX LPTX
142: [ZADD] [LO R],[AR]
143: [ZPUSH] [REGNO CS]
144: [ZPOP] [HI R]
145:
146: % PLVALUE
147: LPTX ANYL LOTEMP * TEMP
148: TREG WORD
149: ADS|MMX LPTX
150: [ZADD] [LO R],[AR]
151: [ZPUSH] [REGNO DS]
152: [ZPOP] [HI R]
153:
154: % PEFFECT|PRVALUE
155: LPTX DXAX AX * DXAX
156: TREG WORD
157: REG|MMX LPTX
158: [ZADD] [LO R],[LO AR]
159: [ZMOV] [HI R],[HI AR]
160:
161: % PLVALUE
162: LPTX ANYL LOTEMP * TEMP
163: TREG WORD
164: REG|MMX LPTX
165: [ZADD] [LO R],[LO AR]
166: [ZPUSH] [HI AR]
167: [ZPOP] [HI R]
168:
169: % PEFFECT|PRVALUE
170: LPTX DXAX AX * DXAX
171: TREG WORD
172: ADR LPTX
173: % PLVALUE
174: LPTX ANYL LOTEMP * TEMP
175: TREG WORD
176: ADR LPTX
177: [ZADD] [LO R],[LO AR]
178: [ZMOV] [HI R],[HI AR]
179: #endif
180:
181: % PEFFECT|PRVALUE|PGE|PLT|P_SLT
182: LONG DXAX DXAX * DXAX
183: TREG LONG
184: ADR|IMM LONG
185: [ZADD] [LO R],[LO AR]
186: [ZADC] [HI R],[HI AR]
187: [IFR] [REL1] [LAB]
188:
189: #ifndef ONLYSMALL
190: % PEFFECT|PRVALUE|P_SLT
191: LPTX ANYR ANYR * TEMP
192: TREG LPTX
193: ADR|IMM LONG
194: % PLVALUE|P_SLT
195: LPTX ANYL ANYL * TEMP
196: TREG LPTX
197: ADR|IMM LONG
198: [ZADD] [LO R],[LO AR]
199:
200: % PEFFECT|PRVALUE
201: LPTX DXAX DXAX * DXAX
202: TREG LONG
203: ADR|IMM LPTX
204: % PLVALUE
205: LPTX ESAX DXAX * DXAX
206: TREG LONG
207: ADR|IMM LPTX
208: [ZADD] [LO R],[LO AR]
209: [ZMOV] [HI R],[HI AR]
210: #endif
211:
212: /////////
213: /
214: / These special table entries make pushing offsts into structures and
215: / arrays more efficient. In particular, they improve the code for some of
216: / the standard I/O macros, when aimed at constant streams (like the stdin,
217: / stdout and stder streams).
218: /
219: /////////
220:
221: #ifndef ONLYSMALL
222: % PFNARG
223: LPTX AX * * NONE
224: ADR LPTX
225: IMM|MMX WORD
226: [ZPUSH] [HI AL]
227: [ZMOV] [R],[LO AL]
228: [ZADD] [R],[AR]
229: [ZPUSH] [R]
230:
231: % PFNARG
232: LPTX AX * * NONE
233: IMM|MMX WORD
234: ADR LPTX
235: [ZPUSH] [HI AR]
236: [ZMOV] [R],[LO AR]
237: [ZADD] [R],[AL]
238: [ZPUSH] [R]
239: #endif
240:
241: ////////
242: /
243: / Floating point, using the numeric
244: / data coprocessor (8087).
245: /
246: ////////
247:
248: #ifdef NDPDEF
249: % PRVALUE|P_SLT
250: FF32|FF64 FPAC FPAC * FPAC
251: TREG FF64
252: ADR FS16
253: [ZFADDI] [AR]
254:
255: % PRVALUE|P_SLT
256: FF32|FF64 FPAC FPAC * FPAC
257: TREG FF64
258: ADR FS32
259: [ZFADDL] [AR]
260:
261: % PRVALUE|P_SLT
262: FF32|FF64 FPAC FPAC * FPAC
263: TREG FF64
264: ADR FF32
265: [ZFADDF] [AR]
266:
267: % PRVALUE|P_SLT
268: FF32|FF64 FPAC FPAC * FPAC
269: TREG FF64
270: ADR FF64
271: [ZFADDD] [AR]
272: #endif
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