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1.1 root 1: /////////
2: /
3: / Assigned divide. This table does not do doubles yet. It does have to
4: / handle fields; the right hand operand of the field is not preshifted
5: / like it is for add, subtract and the increment/decrement ops.
6: /
7: /////////
8:
9: ADIV:
10: % PEFFECT|PRVALUE
11: WORD DXAX * * AX
12: ADR|LV FS16
13: ADR WORD
14: [ZMOV] [LO R],[AL]
15: [ZCWD]
16: [ZIDIV] [AR]
17: [ZMOV] [AL],[LO R]
18:
19: % PEFFECT|PRVALUE
20: WORD DXAX * * AX
21: ADR|LV FU16
22: ADR WORD
23: [ZMOV] [LO R],[AL]
24: [ZSUB] [HI R],[HI R]
25: [ZDIV] [AR]
26: [ZMOV] [AL],[LO R]
27:
28: % PEFFECT|PRVALUE
29: WORD DXAX * * AX
30: ADR|LV FFLD16
31: ADR WORD
32: [ZMOV] [LO R],[AL]
33: [ZAND] [LO R],[LO EMASK]
34: [ZSUB] [HI R],[HI R]
35: [ZDIV] [AR]
36: [ZAND] [LO R],[LO EMASK]
37: [ZAND] [AL],[LO CMASK]
38: [ZOR] [AL],[LO R]
39:
40: % PEFFECT|PRVALUE
41: WORD DXAX * * AX
42: ADR|LV FS8
43: ADR WORD
44: [ZMOVB] [LO LO R],[AL]
45: [ZCBW]
46: [ZCWD]
47: [ZIDIV] [AR]
48: [ZMOVB] [AL],[LO LO R]
49: [IFV] [ZCBW]
50:
51: % PEFFECT|PRVALUE
52: WORD DXAX * * AX
53: ADR|LV FU8
54: ADR WORD
55: [ZMOVB] [LO LO R],[AL]
56: [ZSUBB] [HI LO R],[HI LO R]
57: [ZCWD]
58: [ZDIV] [AR]
59: [ZMOVB] [AL],[LO LO R]
60: [IFV] [ZSUBB] [HI LO R],[HI LO R]
61:
62: % PEFFECT|PRVALUE
63: WORD DXAX * * AX
64: ADR|LV FFLD8
65: ADR WORD
66: [ZMOVB] [LO LO R],[AL]
67: [ZAND] [LO R],[LO EMASK] / Zero AH.
68: [ZSUB] [HI R],[HI R]
69: [ZDIV] [AR]
70: [ZAND] [LO R],[LO EMASK]
71: [ZANDB] [AL],[LO CMASK]
72: [ZORB] [AL],[LO LO R]
73:
74: % PEFFECT|PRVALUE
75: LONG DXAX * DXAX DXAX
76: ADR|LV FS32
77: TREG LONG
78: [ZPUSH] [HI R]
79: [ZPUSH] [LO R]
80: [ZPUSH] [HI AL]
81: [ZPUSH] [LO AL]
82: [CALL] [GID lrdiv]
83: [ZADD] [REGNO SP],[CONST 8]
84: [ZMOV] [LO AL],[LO R]
85: [ZMOV] [HI AL],[HI R]
86:
87: % PEFFECT|PRVALUE
88: LONG DXAX * DXAX DXAX
89: ADR|LV FU32
90: TREG LONG
91: [ZPUSH] [HI R]
92: [ZPUSH] [LO R]
93: [ZPUSH] [HI AL]
94: [ZPUSH] [LO AL]
95: [CALL] [GID vrdiv]
96: [ZADD] [REGNO SP],[CONST 8]
97: [ZMOV] [LO AL],[LO R]
98: [ZMOV] [HI AL],[HI R]
99:
100: % PEFFECT|PRVALUE
101: LONG DXAX * * DXAX
102: ADR|LV FS32
103: ADR LONG
104: [ZPUSH] [HI AR]
105: [ZPUSH] [LO AR]
106: [ZPUSH] [HI AL]
107: [ZPUSH] [LO AL]
108: [CALL] [GID lrdiv]
109: [ZADD] [REGNO SP],[CONST 8]
110: [ZMOV] [LO AL],[LO R]
111: [ZMOV] [HI AL],[HI R]
112:
113: % PEFFECT|PRVALUE
114: LONG DXAX * * DXAX
115: ADR|LV FU32
116: ADR LONG
117: [ZPUSH] [HI AR]
118: [ZPUSH] [LO AR]
119: [ZPUSH] [HI AL]
120: [ZPUSH] [LO AL]
121: [CALL] [GID vrdiv]
122: [ZADD] [REGNO SP],[CONST 8]
123: [ZMOV] [LO AL],[LO R]
124: [ZMOV] [HI AL],[HI R]
125:
126: ////////
127: /
128: / Floating point, using the numeric
129: / data coprocessor (8087).
130: /
131: ////////
132:
133: #ifdef NDPDEF
134: % PEFFECT|PRVALUE
135: FF32|FF64 FPAC * FPAC FPAC
136: ADR|LV FF32
137: TREG FF64
138: [ZFRDIVF] [AL]
139: [IFV] [ZFSTF] [AL]
140: [IFE] [ZFSTPF] [AL]
141:
142: % PEFFECT|PRVALUE
143: FF32|FF64 FPAC * FPAC FPAC
144: ADR|LV FF64
145: TREG FF64
146: [ZFRDIVD] [AL]
147: [IFV] [ZFSTD] [AL]
148: [IFE] [ZFSTPD] [AL]
149: #endif
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