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1.1 root 1: /////////
2: /
3: / Assigned multiply.
4: / Not a lot of special cases. The fixed register requirements of
5: / byte operations and the multiply instruction make it not very
6: / necessary. Also handles fields.
7: /
8: /////////
9:
10: AMUL:
11: % PEFFECT|PRVALUE|PLVALUE|P80186
12: WORD ANYR * * TEMP
13: ADR|LV WORD
14: IMM|MMX WORD
15: [ZIMULI] [R],[AL],[AR]
16: [ZMOV] [AL],[R]
17:
18: % PEFFECT|PRVALUE|PLVALUE
19: WORD DXAX * * AX
20: ADR|LV FS16
21: ADR WORD
22: [ZMOV] [LO R],[AL]
23: [ZIMUL] [AR]
24: [ZMOV] [AL],[LO R]
25:
26: % PEFFECT|PRVALUE|PLVALUE
27: WORD DXAX * * AX
28: ADR|LV UWORD
29: ADR WORD
30: [ZMOV] [LO R],[AL]
31: [ZMUL] [AR]
32: [ZMOV] [AL],[LO R]
33:
34: % PEFFECT|PRVALUE
35: WORD DXAX * * AX
36: ADR|LV FFLD16
37: ADR WORD
38: [ZMOV] [LO R],[AL]
39: [ZAND] [LO R],[LO EMASK]
40: [ZMUL] [AR]
41: [ZAND] [LO R],[LO EMASK]
42: [ZAND] [AL],[LO CMASK]
43: [ZOR] [AL],[LO R]
44:
45: % PEFFECT|PRVALUE
46: WORD DXAX * * AX
47: ADR|LV FS8
48: ADR WORD
49: [ZMOVB] [LO LO R],[AL]
50: [ZCBW]
51: [ZIMUL] [AR]
52: [ZMOVB] [AL],[LO LO R]
53: [IFV] [ZCBW]
54:
55: % PEFFECT|PRVALUE
56: WORD DXAX * * AX
57: ADR|LV FU8
58: ADR WORD
59: [ZMOVB] [LO LO R],[AL]
60: [ZSUBB] [HI LO R],[HI LO R]
61: [ZMUL] [AR]
62: [ZMOVB] [AL],[LO LO R]
63: [IFV] [ZSUBB] [HI LO R],[HI LO R]
64:
65: % PEFFECT|PRVALUE
66: WORD DXAX * * AX
67: ADR|LV FFLD8
68: ADR WORD
69: [ZMOVB] [LO LO R],[AL]
70: [ZAND] [LO R],[LO EMASK] / Clear AH too.
71: [ZMUL] [AR]
72: [ZAND] [LO R],[LO EMASK]
73: [ZANDB] [AL],[LO CMASK]
74: [ZORB] [AL],[LO LO R]
75:
76: % PEFFECT|PRVALUE
77: LONG DXAX * DXAX DXAX
78: ADR|LV FS32
79: TREG LONG
80: [ZPUSH] [HI R]
81: [ZPUSH] [LO R]
82: [ZPUSH] [HI AL]
83: [ZPUSH] [LO AL]
84: [CALL] [GID lrmul]
85: [ZADD] [REGNO SP],[CONST 8]
86: [ZMOV] [LO AL],[LO R]
87: [ZMOV] [HI AL],[HI R]
88:
89: % PEFFECT|PRVALUE
90: LONG DXAX * DXAX DXAX
91: ADR|LV FU32
92: TREG LONG
93: [ZPUSH] [HI R]
94: [ZPUSH] [LO R]
95: [ZPUSH] [HI AL]
96: [ZPUSH] [LO AL]
97: [CALL] [GID vrmul]
98: [ZADD] [REGNO SP],[CONST 8]
99: [ZMOV] [LO AL],[LO R]
100: [ZMOV] [HI AL],[HI R]
101:
102: % PEFFECT|PRVALUE
103: LONG DXAX * * DXAX
104: ADR|LV FS32
105: ADR LONG
106: [ZPUSH] [HI AR]
107: [ZPUSH] [LO AR]
108: [ZPUSH] [HI AL]
109: [ZPUSH] [LO AL]
110: [CALL] [GID lrmul]
111: [ZADD] [REGNO SP],[CONST 8]
112: [ZMOV] [LO AL],[LO R]
113: [ZMOV] [HI AL],[HI R]
114:
115: % PEFFECT|PRVALUE
116: LONG DXAX * * DXAX
117: ADR|LV FU32
118: ADR LONG
119: [ZPUSH] [HI AR]
120: [ZPUSH] [LO AR]
121: [ZPUSH] [HI AL]
122: [ZPUSH] [LO AL]
123: [CALL] [GID vrmul]
124: [ZADD] [REGNO SP],[CONST 8]
125: [ZMOV] [LO AL],[LO R]
126: [ZMOV] [HI AL],[HI R]
127:
128: ////////
129: /
130: / Floating point, using the numeric
131: / data coprocessor (8087).
132: /
133: ////////
134:
135: #ifdef NDPDEF
136: % PEFFECT|PRVALUE
137: FF32|FF64 FPAC * FPAC FPAC
138: ADR|LV FF32
139: TREG FF64
140: [ZFMULF] [AL]
141: [IFV] [ZFSTF] [AL]
142: [IFE] [ZFSTPF] [AL]
143:
144: % PEFFECT|PRVALUE
145: FF32|FF64 FPAC * FPAC FPAC
146: ADR|LV FF64
147: TREG FF64
148: [ZFMULD] [AL]
149: [IFV] [ZFSTD] [AL]
150: [IFE] [ZFSTPD] [AL]
151: #endif
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