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1.1 root 1: /////////
2: /
3: / Assigned shift left.
4: / Simple cases (1, 2 on 8086, byte immediates on 186/286) are done directly.
5: / Hard words are done using the CL shift mode. Longs are a loop.
6: / The loop always runs in the registers to make it run faster.
7: / The MOVB gambit is played here to save a byte.
8: /
9: /////////
10:
11: ASHL:
12: % PEFFECT|PRVALUE|PREL|P80186
13: WORD ANYR * * TEMP
14: ADR|LV WORD
15: BYTE|MMX WORD
16: % PLVALUE|P80186
17: WORD ANYL * * TEMP
18: ADR|LV WORD
19: BYTE|MMX WORD
20: [ZSAL] [AL],[AR]
21: [IFV] [ZMOV] [R],[AL]
22: [IFR] [REL0] [LAB]
23:
24: % PEFFECT|PRVALUE|PREL|P80186
25: WORD AX * * TEMP
26: ADR|LV FS8
27: BYTE|MMX WORD
28: [ZSALB] [AL],[AR]
29: [IFV] [ZMOVB] [LO R],[AL]
30: [IFV] [ZCBW]
31: [IFR] [REL0] [LAB]
32:
33: % PEFFECT|PRVALUE|PREL|P80186
34: WORD AX * * TEMP
35: ADR|LV FU8
36: BYTE|MMX WORD
37: [ZSALB] [AL],[AR]
38: [IFV] [ZMOVB] [LO R],[AL]
39: [IFV] [ZSUBB] [HI R],[HI R]
40: [IFR] [REL0] [LAB]
41:
42: % PEFFECT|PRVALUE|PREL
43: WORD ANYR * * TEMP
44: ADR|LV WORD
45: 1|MMX *
46: % PLVALUE
47: WORD ANYL * * TEMP
48: ADR|LV WORD
49: 1|MMX *
50: [ZSAL] [AL],[CONST 1]
51: [IFV] [ZMOV] [R],[AL]
52: [IFR] [REL0] [LAB]
53:
54: % PEFFECT|PRVALUE|PREL
55: WORD AX * * TEMP
56: ADR|LV FS8
57: 1|MMX *
58: [ZSALB] [AL],[CONST 1]
59: [IFV] [ZMOVB] [LO R],[AL]
60: [IFV] [ZCBW]
61: [IFR] [REL0] [LAB]
62:
63: % PEFFECT|PRVALUE|PREL
64: WORD AX * * TEMP
65: ADR|LV FU8
66: 1|MMX *
67: [ZSALB] [AL],[CONST 1]
68: [IFV] [ZMOVB] [LO R],[AL]
69: [IFV] [ZSUBB] [HI R],[HI R]
70: [IFR] [REL0] [LAB]
71:
72: % PEFFECT|PRVALUE|PREL
73: WORD ANYR * * TEMP
74: ADR|LV WORD
75: 2|MMX *
76: % PLVALUE
77: WORD ANYL * * TEMP
78: ADR|LV WORD
79: 2|MMX *
80: [ZSAL] [AL],[CONST 1]
81: [ZSAL] [AL],[CONST 1]
82: [IFV] [ZMOV] [R],[AL]
83: [IFR] [REL0] [LAB]
84:
85: % PEFFECT|PRVALUE|PREL
86: WORD AX * * TEMP
87: ADR|LV FS8
88: 2|MMX *
89: [ZSALB] [AL],[CONST 1]
90: [ZSALB] [AL],[CONST 1]
91: [IFV] [ZMOVB] [LO R],[AL]
92: [IFV] [ZCBW]
93: [IFR] [REL0] [LAB]
94:
95: % PEFFECT|PRVALUE|PREL
96: WORD AX * * TEMP
97: ADR|LV FU8
98: 2|MMX *
99: [ZSALB] [AL],[CONST 1]
100: [ZSALB] [AL],[CONST 1]
101: [IFV] [ZMOVB] [LO R],[AL]
102: [IFV] [ZSUBB] [HI R],[HI R]
103: [IFR] [REL0] [LAB]
104:
105: % PEFFECT|PRVALUE|PREL
106: WORD ANYR * CX TEMP
107: ADR|LV WORD
108: IMM|MMX WORD
109: % PLVALUE
110: WORD ANYL * CX TEMP
111: ADR|LV WORD
112: IMM|MMX WORD
113: [ZMOVB] [REGNO CL],[AR]
114: [ZSAL] [AL],[REGNO CL]
115: [IFV] [ZMOV] [R],[AL]
116: [IFR] [REL0] [LAB]
117:
118: % PEFFECT|PRVALUE|PREL
119: WORD AX * CX TEMP
120: ADR|LV FS8
121: IMM|MMX WORD
122: [ZMOVB] [REGNO CL],[AR]
123: [ZSALB] [AL],[REGNO CL]
124: [IFV] [ZMOVB] [LO R],[AL]
125: [IFV] [ZCBW]
126: [IFR] [REL0] [LAB]
127:
128: % PEFFECT|PRVALUE|PREL
129: WORD AX * CX TEMP
130: ADR|LV FU8
131: IMM|MMX WORD
132: [ZMOVB] [REGNO CL],[AR]
133: [ZSALB] [AL],[REGNO CL]
134: [IFV] [ZMOVB] [LO R],[AL]
135: [IFV] [ZSUBB] [HI R],[HI R]
136: [IFR] [REL0] [LAB]
137:
138: % PRVALUE|PLT|PGE
139: LONG DXAX * CX TEMP
140: ADR|LV LONG
141: IMM|MMX WORD
142: [ZMOV] [REGNO CX],[AR]
143: [ZMOV] [LO R],[LO AL]
144: [ZMOV] [HI R],[HI AL]
145: [DLAB0]:[ZSAL] [LO R],[CONST 1]
146: [ZRCL] [HI R],[CONST 1]
147: [ZLOOP] [LAB0]
148: [ZMOV] [LO AL],[LO R]
149: [ZMOV] [HI AL],[HI R]
150: [IFR] [REL1] [LAB]
151:
152: % PEFFECT|PRVALUE
153: WORD ANYR * CX TEMP
154: ADR|LV WORD
155: ADR WORD
156: [ZMOV] [REGNO CX],[AR]
157: [ZSAL] [AL],[REGNO CL]
158: [IFV] [ZMOV] [R],[AL]
159:
160: % PEFFECT|PRVALUE
161: WORD AX * CX TEMP
162: ADR|LV FS8
163: ADR WORD
164: [ZMOV] [REGNO CX],[AR]
165: [ZSALB] [AL],[REGNO CL]
166: [IFV] [ZMOVB] [LO R],[AL]
167: [IFV] [ZCBW]
168:
169: % PEFFECT|PRVALUE
170: WORD AX * CX TEMP
171: ADR|LV FU8
172: ADR WORD
173: [ZMOV] [REGNO CX],[AR]
174: [ZSALB] [AL],[REGNO CL]
175: [IFV] [ZMOVB] [LO R],[AL]
176: [IFV] [ZSUBB] [HI R],[HI R]
177:
178: % PRVALUE
179: LONG DXAX * CX TEMP
180: ADR|LV LONG
181: ADR WORD
182: [ZMOV] [REGNO CX],[AR]
183: [ZMOV] [LO R],[LO AL]
184: [ZMOV] [HI R],[HI AL]
185: [ZJCXZ] [LAB0]
186: [DLAB1]:[ZSAL] [LO R],[CONST 1]
187: [ZRCL] [HI R],[CONST 1]
188: [ZLOOP] [LAB1]
189: [ZMOV] [LO AL],[LO R]
190: [ZMOV] [HI AL],[HI R]
191: [DLAB0]:
192:
193: % PEFFECT|PRVALUE|P80186
194: WORD ANYR * * TEMP
195: ADR|LV FFLD16
196: BYTE|MMX WORD
197: [ZMOV] [R],[AL]
198: [ZAND] [R],[LO EMASK]
199: [ZSHL] [R],[AR]
200: [ZAND] [R],[LO EMASK]
201: [ZAND] [AL],[LO CMASK]
202: [ZOR] [AL],[R]
203:
204: % PEFFECT|PRVALUE|P80186
205: WORD AX * * TEMP
206: ADR|LV FFLD8
207: BYTE|MMX WORD
208: [ZMOVB] [LO R],[AL]
209: [ZANDB] [LO R],[LO EMASK]
210: [ZSHLB] [LO R],[AR]
211: [ZAND] [R],[LO EMASK]
212: [ZANDB] [AL],[LO CMASK]
213: [ZORB] [AL],[LO R]
214:
215: % PEFFECT|PRVALUE
216: WORD ANYR * * TEMP
217: ADR|LV FFLD16
218: 1|MMX *
219: [ZMOV] [R],[AL]
220: [ZAND] [R],[LO EMASK]
221: [ZSHL] [R],[AR]
222: [ZAND] [R],[LO EMASK]
223: [ZAND] [AL],[LO CMASK]
224: [ZOR] [AL],[R]
225:
226: % PEFFECT|PRVALUE
227: WORD AX * * TEMP
228: ADR|LV FFLD8
229: 1|MMX *
230: [ZMOVB] [LO R],[AL]
231: [ZANDB] [LO R],[LO EMASK]
232: [ZSHLB] [LO R],[AR]
233: [ZAND] [R],[LO EMASK]
234: [ZANDB] [AL],[LO CMASK]
235: [ZORB] [AL],[LO R]
236:
237: % PEFFECT|PRVALUE
238: WORD ANYR * * TEMP
239: ADR|LV FFLD16
240: 2|MMX *
241: [ZMOV] [R],[AL]
242: [ZAND] [R],[LO EMASK]
243: [ZSHL] [R],[CONST 1]
244: [ZSHL] [R],[CONST 1]
245: [ZAND] [R],[LO EMASK]
246: [ZAND] [AL],[LO CMASK]
247: [ZOR] [AL],[R]
248:
249: % PEFFECT|PRVALUE
250: WORD AX * * TEMP
251: ADR|LV FFLD8
252: 2|MMX *
253: [ZMOVB] [LO R],[AL]
254: [ZANDB] [LO R],[LO EMASK]
255: [ZSHLB] [LO R],[CONST 1]
256: [ZSHLB] [LO R],[CONST 1]
257: [ZAND] [R],[LO EMASK]
258: [ZANDB] [AL],[LO CMASK]
259: [ZORB] [AL],[LO R]
260:
261: % PEFFECT|PRVALUE
262: WORD ANYR * CX TEMP
263: ADR|LV FFLD16
264: IMM|MMX WORD
265: [ZMOV] [R],[AL]
266: [ZAND] [R],[LO EMASK]
267: [ZMOVB] [REGNO CL],[AR]
268: [ZSHL] [R],[REGNO CL]
269: [ZAND] [R],[LO EMASK]
270: [ZAND] [AL],[LO CMASK]
271: [ZOR] [AL],[R]
272:
273: % PEFFECT|PRVALUE
274: WORD AX * CX TEMP
275: ADR|LV FFLD8
276: IMM|MMX WORD
277: [ZMOVB] [LO R],[AL]
278: [ZANDB] [LO R],[LO EMASK]
279: [ZMOVB] [REGNO CL],[AR]
280: [ZSHLB] [LO R],[REGNO CL]
281: [ZAND] [R],[LO EMASK]
282: [ZANDB] [AL],[LO CMASK]
283: [ZORB] [AL],[LO R]
284:
285: % PEFFECT|PRVALUE
286: WORD ANYR * CX TEMP
287: ADR|LV FFLD16
288: ADR WORD
289: [ZMOV] [R],[AL]
290: [ZAND] [R],[LO EMASK]
291: [ZMOV] [REGNO CX],[AR]
292: [ZSHL] [R],[REGNO CL]
293: [ZAND] [R],[LO EMASK]
294: [ZAND] [AL],[LO CMASK]
295: [ZOR] [AL],[R]
296:
297: % PEFFECT|PRVALUE
298: WORD AX * CX TEMP
299: ADR|LV FFLD8
300: ADR WORD
301: [ZMOVB] [LO R],[AL]
302: [ZANDB] [LO R],[LO EMASK]
303: [ZMOV] [REGNO CX],[AR]
304: [ZSHLB] [LO R],[REGNO CL]
305: [ZAND] [R],[LO EMASK]
306: [ZANDB] [AL],[LO CMASK]
307: [ZORB] [AL],[LO R]
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