coherent/b/bin/c/n1/i8086/tables/ashr.t - view

File: [MW Coherent from dump] / coherent / b / bin / c / n1 / i8086 / tables / ashr.t
Revision 1.1.1.1 (vendor branch): download - view: text, annotated - select for diffs
Wed May 29 04:56:37 2019 UTC (7 years, 2 months ago) by root
Branches: MarkWilliams, MAIN
CVS tags: relic, HEAD

coherent

///////// / / Assigned shift right is just like assigned shift left, except / there are more cases because different code is generated for signed / and unsigned left values. The simple cases are optimized. The game / that uses a MOVB to load the constant value of a shift loop counter / is also played. / ///////// ASHR: % PEFFECT|PRVALUE|PREL|P80186 WORD ANYR * * TEMP ADR|LV FS16 BYTE|MMX WORD [ZSAR] [AL],[AR] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL|P80186 WORD ANYR * * TEMP ADR|LV UWORD BYTE|MMX WORD [ZSHR] [AL],[AR] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|P80186 WORD ANYR * * TEMP ADR|LV FFLD16 BYTE|MMX WORD [ZMOV] [R],[AL] [ZAND] [R],[LO EMASK] [ZSHR] [R],[AR] [ZAND] [R],[LO EMASK] [ZAND] [AL],[LO CMASK] [ZOR] [AL],[R] % PEFFECT|PRVALUE|PREL|P80186 WORD AX * * TEMP ADR|LV FS8 BYTE|MMX WORD [ZSARB] [AL],[AR] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZCBW] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL|P80186 WORD AX * * TEMP ADR|LV FU8 BYTE|MMX WORD [ZSHRB] [AL],[AR] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZSUBB] [HI R],[HI R] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|P80186 WORD AX * * TEMP ADR|LV FFLD8 BYTE|MMX WORD [ZMOVB] [LO R],[AL] [ZANDB] [LO R],[LO EMASK] [ZSHRB] [LO R],[AR] [ZAND] [R],[LO EMASK] [ZANDB] [AL],[LO CMASK] [ZORB] [AL],[LO R] % PEFFECT|PRVALUE|PREL WORD ANYR * * TEMP ADR|LV FS16 1|MMX * [ZSAR] [AL],[AR] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL WORD ANYR * * TEMP ADR|LV UWORD 1|MMX * [ZSHR] [AL],[AR] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE WORD ANYR * * TEMP ADR|LV FFLD16 1|MMX * [ZMOV] [R],[AL] [ZAND] [R],[LO EMASK] [ZSHR] [R],[AR] [ZAND] [R],[LO EMASK] [ZAND] [AL],[LO CMASK] [ZOR] [AL],[R] % PEFFECT|PRVALUE|PREL WORD AX * * TEMP ADR|LV FS8 1|MMX * [ZSARB] [AL],[AR] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZCBW] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL WORD AX * * TEMP ADR|LV FU8 1|MMX * [ZSHRB] [AL],[AR] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZSUBB] [HI R],[HI R] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE WORD AX * * TEMP ADR|LV FFLD8 1|MMX * [ZMOVB] [LO R],[AL] [ZANDB] [LO R],[LO EMASK] [ZSHRB] [LO R],[AR] [ZAND] [R],[LO EMASK] [ZANDB] [AL],[LO CMASK] [ZORB] [AL],[LO R] % PEFFECT|PRVALUE LONG DXAX * * TEMP ADR|LV FS32 1|MMX * [ZSAR] [HI AL],[AR] [ZRCR] [LO AL],[AR] [IFV] [ZMOV] [LO R],[LO AL] [IFV] [ZMOV] [HI R],[HI AL] % PEFFECT|PRVALUE LONG DXAX * * TEMP ADR|LV FU32 1|MMX * [ZSHR] [HI AL],[AR] [ZRCR] [LO AL],[AR] [IFV] [ZMOV] [LO R],[LO AL] [IFV] [ZMOV] [HI R],[HI AL] % PEFFECT|PRVALUE|PREL WORD ANYR * * TEMP ADR|LV FS16 2|MMX * [ZSAR] [AL],[CONST 1] [ZSAR] [AL],[CONST 1] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL WORD ANYR * * TEMP ADR|LV UWORD 2|MMX * [ZSHR] [AL],[CONST 1] [ZSHR] [AL],[CONST 1] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE WORD ANYR * * TEMP ADR|LV FFLD16 2|MMX * [ZMOV] [R],[AL] [ZAND] [R],[LO EMASK] [ZSHR] [R],[CONST 1] [ZSHR] [R],[CONST 1] [ZAND] [R],[LO EMASK] [ZAND] [AL],[LO CMASK] [ZOR] [AL],[R] % PEFFECT|PRVALUE|PREL WORD AX * * TEMP ADR|LV FS8 2|MMX * [ZSARB] [AL],[CONST 1] [ZSARB] [AL],[CONST 1] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZCBW] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL WORD AX * * TEMP ADR|LV FU8 2|MMX * [ZSHRB] [AL],[CONST 1] [ZSHRB] [AL],[CONST 1] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZSUBB] [HI R],[HI R] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE WORD AX * * TEMP ADR|LV FFLD8 2|MMX * [ZMOVB] [LO R],[AL] [ZANDB] [LO R],[LO EMASK] [ZSHRB] [LO R],[CONST 1] [ZSHRB] [LO R],[CONST 1] [ZAND] [R],[LO EMASK] [ZANDB] [AL],[LO CMASK] [ZORB] [AL],[LO R] % PEFFECT|PRVALUE|PREL WORD ANYR * CX TEMP ADR|LV FS16 IMM|MMX WORD [ZMOVB] [REGNO CL],[AR] [ZSAR] [AL],[REGNO CL] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL WORD ANYR * CX TEMP ADR|LV UWORD IMM|MMX WORD [ZMOVB] [REGNO CL],[AR] [ZSHR] [AL],[REGNO CL] [IFV] [ZMOV] [R],[AL] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE WORD ANYR * CX TEMP ADR|LV FFLD16 IMM|MMX WORD [ZMOV] [R],[AL] [ZAND] [R],[LO EMASK] [ZMOVB] [REGNO CL],[AR] [ZSHR] [R],[REGNO CL] [ZAND] [R],[LO EMASK] [ZAND] [AL],[LO CMASK] [ZOR] [AL],[R] % PEFFECT|PRVALUE|PREL WORD AX * CX TEMP ADR|LV FS8 IMM|MMX WORD [ZMOVB] [REGNO CL],[AR] [ZSARB] [AL],[REGNO CL] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZCBW] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE|PREL WORD AX * CX TEMP ADR|LV FU8 IMM|MMX WORD [ZMOVB] [REGNO CL],[AR] [ZSHRB] [AL],[REGNO CL] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZSUBB] [HI R],[HI R] [IFR] [REL0] [LAB] % PEFFECT|PRVALUE WORD AX * CX TEMP ADR|LV FFLD8 IMM|MMX WORD [ZMOVB] [LO R],[AL] [ZANDB] [LO R],[LO EMASK] [ZMOVB] [REGNO CL],[AR] [ZSHRB] [LO R],[REGNO CL] [ZAND] [R],[LO EMASK] [ZANDB] [AL],[LO CMASK] [ZORB] [AL],[LO R] % PRVALUE|PLT|PGE LONG DXAX * CX TEMP ADR|LV FS32 IMM|MMX WORD [ZMOV] [REGNO CX],[AR] [ZMOV] [LO R],[LO AL] [ZMOV] [HI R],[HI AL] [DLAB0]:[ZSAR] [HI R],[CONST 1] [ZRCR] [LO R],[CONST 1] [ZLOOP] [LAB0] [ZMOV] [LO AL],[LO R] [ZMOV] [HI AL],[HI R] [IFR] [REL1] [LAB] % PRVALUE|PLT|PGE LONG DXAX * CX DXAX ADR|LV FU32 IMM|MMX WORD [ZMOV] [REGNO CX],[AR] [ZMOV] [LO R],[LO AL] [ZMOV] [HI R],[HI AL] [DLAB0]:[ZSHR] [HI R],[CONST 1] [ZRCR] [LO R],[CONST 1] [ZLOOP] [LAB0] [ZMOV] [LO AL],[LO R] [ZMOV] [HI AL],[HI R] [IFR] [REL1] [LAB] % PEFFECT|PRVALUE WORD ANYR * CX TEMP ADR|LV FS16 ADR WORD [ZMOV] [REGNO CX],[AR] [ZSAR] [AL],[REGNO CL] [IFV] [ZMOV] [R],[AL] % PEFFECT|PRVALUE WORD ANYR * CX TEMP ADR|LV UWORD ADR WORD [ZMOV] [REGNO CX],[AR] [ZSHR] [AL],[REGNO CL] [IFV] [ZMOV] [R],[AL] % PEFFECT|PRVALUE WORD ANYR * CX TEMP ADR|LV FFLD16 ADR WORD [ZMOV] [R],[AL] [ZAND] [R],[LO EMASK] [ZMOV] [REGNO CX],[AR] [ZSHR] [R],[REGNO CL] [ZAND] [R],[LO EMASK] [ZAND] [AL],[LO CMASK] [ZOR] [AL],[R] % PEFFECT|PRVALUE WORD AX * CX TEMP ADR|LV FS8 ADR WORD [ZMOV] [REGNO CX],[AR] [ZSARB] [AL],[REGNO CL] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZCBW] % PEFFECT|PRVALUE WORD AX * CX TEMP ADR|LV FU8 ADR WORD [ZMOV] [REGNO CX],[AR] [ZSHRB] [AL],[REGNO CL] [IFV] [ZMOVB] [LO R],[AL] [IFV] [ZSUBB] [HI R],[HI R] % PEFFECT|PRVALUE WORD AX * CX TEMP ADR|LV FFLD8 ADR WORD [ZMOVB] [LO R],[AL] [ZANDB] [LO R],[LO EMASK] [ZMOV] [REGNO CX],[AR] [ZSHRB] [LO R],[REGNO CL] [ZAND] [R],[LO EMASK] [ZANDB] [AL],[LO CMASK] [ZORB] [AL],[LO R] % PRVALUE LONG DXAX * CX TEMP ADR|LV FS32 ADR WORD [ZMOV] [REGNO CX],[AR] [ZMOV] [LO R],[LO AL] [ZMOV] [HI R],[HI AL] [ZJCXZ] [LAB0] [DLAB1]:[ZSAR] [HI R],[CONST 1] [ZRCR] [LO R],[CONST 1] [ZLOOP] [LAB1] [ZMOV] [LO AL],[LO R] [ZMOV] [HI AL],[HI R] [DLAB0]: % PRVALUE LONG DXAX * CX TEMP ADR|LV FU32 ADR WORD [ZMOV] [REGNO CX],[AR] [ZMOV] [LO R],[LO AL] [ZMOV] [HI R],[HI AL] [ZJCXZ] [LAB0] [DLAB1]:[ZSHR] [HI R],[CONST 1] [ZRCR] [LO R],[CONST 1] [ZLOOP] [LAB1] [ZMOV] [LO AL],[LO R] [ZMOV] [HI AL],[HI R] [DLAB0]:

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