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1.1 root 1: /////////
2: /
3: / Plain and simple assignment. Handles doubles, longs, fields, bytes
4: / and words. This table does not handle doubles. It is not clear if some
5: / kinds of double assignments should be done with move instructions to
6: / save the overhead of loading the 8087 emulator, since the emulator is
7: / big and fat. More complex double assignments, like the ones that must
8: / return a value, use the 8087.
9: / The `=' operator is a non conversion operator for pointers, words and
10: / longs. There must be some special tables here to handle the cross type
11: / cases. This approach makes everything appear to work in a rational
12: / fashion.
13: /
14: /////////
15:
16: ASSIGN:
17: % PEFFECT
18: WORD NONE * * NONE
19: REG|MMX WORD
20: 0|MMX *
21: [ZSUB] [AL],[AL]
22:
23: % PEFFECT
24: WORD NONE * * NONE
25: REG|MMX WORD
26: EASY|MMX WORD
27: % PEFFECT
28: WORD NONE * * NONE
29: ADR|LV WORD
30: REG|MMX WORD
31: % PEFFECT
32: WORD NONE * * NONE
33: ADR|LV WORD
34: IMM|MMX WORD
35: [ZMOV] [AL],[AR]
36:
37: % PEFFECT
38: WORD NONE * * NONE
39: REG|MMX WORD
40: EASY|MMX LONG
41: [ZMOV] [AL],[LO AR]
42:
43: % PEFFECT
44: WORD NONE * * NONE
45: RREG|MMX WORD
46: LEA|MMX WORD
47: [ZLEA] [AL],[NSE AR]
48:
49: % PEFFECT
50: WORD NONE * * NONE
51: ADR|LV BYTE
52: IMM|MMX WORD
53: [ZMOVB] [AL],[AR]
54:
55: % PEFFECT
56: LONG NONE * * NONE
57: ADR|LV LONG
58: IMM|MMX LONG
59: [ZMOV] [LO AL],[LO AR]
60: [ZMOV] [HI AL],[HI AR]
61:
62: % PEFFECT|PRVALUE|PEREL
63: WORD AX * * AX
64: ADR|LV FS8
65: ADR BYTE
66: [ZMOVB] [LO R],[AR]
67: [ZMOVB] [AL],[LO R]
68: [IFV] [ZCBW]
69: [IFR] [ZORB] [LO R],[LO R]
70: [IFR] [REL0] [LAB]
71:
72: % PEFFECT|PRVALUE|PEREL
73: WORD AX * * AX
74: ADR|LV FU8
75: ADR BYTE
76: [ZMOVB] [LO R],[AR]
77: [ZMOVB] [AL],[LO R]
78: [IFV] [ZSUBB] [HI R],[HI R]
79: [IFR] [ZORB] [LO R],[LO R]
80: [IFR] [REL0] [LAB]
81:
82: % PEFFECT
83: WORD AX * * NONE
84: ADR|LV WORD
85: EASY|MMX WORD
86: [ZMOV] [R],[AR]
87: [ZMOV] [AL],[R]
88:
89: % PEFFECT|PRVALUE|P_SRT
90: WORD ANYR * ANYR TEMP
91: ADR|LV WORD
92: TREG WORD
93: % PLVALUE|P_SRT
94: WORD ANYL * ANYL TEMP
95: ADR|LV WORD
96: TREG WORD
97: [ZMOV] [AL],[R]
98:
99: % PEFFECT|PRVALUE|P_SRT
100: WORD AX * AX AX
101: ADR|LV FS8
102: TREG WORD
103: [ZMOVB] [AL],[LO R]
104: [IFV] [ZCBW]
105:
106: % PEFFECT|PRVALUE|P_SRT
107: WORD AX * AX AX
108: ADR|LV FU8
109: TREG WORD
110: [ZMOVB] [AL],[LO R]
111: [IFV] [ZSUBB] [HI R],[HI R]
112:
113: % PRVALUE|P_SRT
114: LONG ANYR * ANYR TEMP
115: ADR|LV LONG
116: TREG LONG
117: [ZMOV] [LO AL],[LO R]
118: [ZMOV] [HI AL],[HI R]
119:
120: % PEFFECT|PRVALUE
121: WORD AX * DXAX AX
122: ADR|LV WORD
123: TREG LONG
124: [ZMOV] [AL],[R]
125:
126: % PEFFECT|PRVALUE|P_SRT
127: WORD DXAX * DXAX AX
128: ADR|LV FS8
129: TREG LONG
130: [ZMOVB] [AL],[LO R]
131: [IFV] [ZCBW]
132:
133: % PEFFECT|PRVALUE|P_SRT
134: WORD DXAX * DXAX AX
135: ADR|LV FU8
136: TREG LONG
137: [ZMOVB] [AL],[LO LO R]
138: [IFV] [ZSUBB] [HI LO R],[HI LO R]
139:
140: /////////
141: /
142: / Assignment between pointers and integer types. These are all set up
143: / as no conversion operations in the parser. We attempt to do a reasonably
144: / good job on the common cases, like setting a pointer to NULL.
145: /
146: /////////
147:
148: #ifndef ONLYSMALL
149: % PEFFECT
150: LPTX NONE * * NONE
151: ADR|LV LPTX
152: 0|MMX *
153: [ZMOV] [LO AL],[CONST 0]
154: [ZMOV] [HI AL],[CONST 0]
155:
156: % PRVALUE
157: LPTX ANYR * * TEMP
158: ADR|LV LPTX
159: 0|MMX *
160: [ZSUB] [LO R],[LO R]
161: [ZMOV] [HI R],[LO R]
162: [ZMOV] [LO AL],[LO R]
163: [ZMOV] [HI AL],[LO R]
164:
165: % PRVALUE
166: LPTX ANYR * * TEMP
167: ADR|LV LPTX
168: ICN|MMX LPTX
169: [ZMOV] [LO R],[AR]
170: [ZSUB] [HI R],[HI R]
171: [ZMOV] [LO AL],[LO R]
172: [ZMOV] [HI AL],[HI R]
173:
174: % PLVALUE|PEFFECT
175: LPTX ANYL * * TEMP
176: ADR|LV LPTX
177: ICN|MMX LPTX
178: [ZMOV] [LO AL],[AR]
179: [ZMOV] [HI AL],[CONST 0]
180: [IFV] [ZLDES] [LO R],[AL]
181:
182: % PRVALUE
183: LPTX ANYR * * TEMP
184: ADR|LV LPTX
185: LCN|MMX LPTX
186: [ZMOV] [LO R],[LO AR]
187: [ZMOV] [HI R],[HI AR]
188: [ZMOV] [LO AL],[LO R]
189: [ZMOV] [HI AL],[HI R]
190:
191: % PLVALUE|PEFFECT
192: LPTX ANYL * * TEMP
193: ADR|LV LPTX
194: LCN|MMX LPTX
195: [ZMOV] [LO AL],[LO AR]
196: [ZMOV] [HI AL],[HI AR]
197: [IFV] [ZLDES] [LO R],[AL]
198:
199: % PRVALUE
200: LPTX ANYR * * TEMP
201: ADR|LV LPTX
202: ACS|MMX LPTX
203: [ZMOV] [LO R],[AR]
204: [ZMOV] [HI R],[REGNO CS]
205: [ZMOV] [LO AL],[LO R]
206: [ZMOV] [HI AL],[HI R]
207:
208: % PRVALUE
209: LPTX ANYR * * TEMP
210: ADR|LV LPTX
211: ADS|MMX LPTX
212: [ZMOV] [LO R],[AR]
213: [ZMOV] [HI R],[REGNO DS]
214: [ZMOV] [LO AL],[LO R]
215: [ZMOV] [HI AL],[HI R]
216:
217: % PLVALUE|PEFFECT
218: LPTX ANYL * * TEMP
219: ADR|LV LPTX
220: ACS|MMX LPTX
221: [ZMOV] [LO AL],[AR]
222: [ZMOV] [HI AL],[REGNO CS]
223: [IFV] [ZLDES] [LO R],[AL]
224:
225: % PLVALUE|PEFFECT
226: LPTX ANYL * * TEMP
227: ADR|LV LPTX
228: ADS|MMX LPTX
229: [ZMOV] [LO AL],[AR]
230: [ZMOV] [HI AL],[REGNO DS]
231: [IFV] [ZLDES] [LO R],[AL]
232:
233: % PRVALUE
234: LPTX ANYR * * TEMP
235: ADR|LV LPTX
236: DIR|MMX WORD
237: [ZMOV] [LO R],[AR]
238: [ZSUB] [HI R],[HI R]
239: [ZMOV] [LO AL],[LO R]
240: [ZMOV] [HI AL],[HI R]
241:
242: % PLVALUE|PEFFECT
243: LPTX ANYL * * TEMP
244: ADR|LV LPTX
245: DIR|MMX WORD
246: [ZMOV] [LO R],[AR]
247: [ZMOV] [LO AL],[LO R]
248: [ZMOV] [HI AL],[CONST 0]
249: [IFV] [ZLDES] [LO R],[AL]
250:
251: % PRVALUE
252: LPTX ANYR * ANYR TEMP
253: ADR|LV LPTX
254: TREG WORD
255: [ZMOV] [LO AL],[RR]
256: [ZMOV] [HI AL],[CONST 0]
257: [ZMOV] [LO R],[LO AL]
258: [ZMOV] [HI R],[HI AL]
259:
260: % PLVALUE|PEFFECT
261: LPTX ANYL * ANYR TEMP
262: ADR|LV LPTX
263: TREG WORD
264: [ZMOV] [LO AL],[RR]
265: [ZMOV] [HI AL],[CONST 0]
266: [IFV] [ZLDES] [LO R],[AL]
267:
268: % PRVALUE
269: LPTX ANYR * * TEMP
270: ADR|LV LPTX
271: DIR|MMX LONG
272: % PRVALUE
273: LONG ANYR * * TEMP
274: ADR|LV LONG
275: DIR|MMX LPTX
276: [ZMOV] [LO R],[LO AR]
277: [ZMOV] [HI R],[HI AR]
278: [ZMOV] [LO AL],[LO R]
279: [ZMOV] [HI AL],[HI R]
280:
281: % PRVALUE
282: LPTX ANYR * ANYR TEMP
283: ADR|LV LPTX
284: TREG LONG
285: [ZMOV] [LO AL],[LO RR]
286: [ZMOV] [HI AL],[HI RR]
287: [ZMOV] [LO R],[LO AL]
288: [ZMOV] [HI R],[HI AL]
289:
290: % PLVALUE|PEFFECT
291: LPTX ANYL * ANYR TEMP
292: ADR|LV LPTX
293: TREG LONG
294: [ZMOV] [LO AL],[LO RR]
295: [ZMOV] [HI AL],[HI RR]
296: [IFV] [ZLDES] [LO R],[AL]
297:
298: % PRVALUE|P_SRT
299: LPTX ANYR * ANYR TEMP
300: ADR|LV LPTX
301: TREG LPTX
302: % PLVALUE|P_SRT
303: LPTX ANYL * ANYL TEMP
304: ADR|LV LPTX
305: TREG LPTX
306: [ZMOV] [LO AL],[LO R]
307: [ZMOV] [HI AL],[HI R]
308:
309: % PRVALUE|PEFFECT|P_SRT
310: LONG ANYR * ANYR TEMP
311: ADR|LV LONG
312: TREG LPTX
313: [ZMOV] [LO AL],[LO RR]
314: [ZMOV] [HI AL],[HI RR]
315:
316: % PRVALUE|PEFFECT
317: WORD ESAX * ESAX AX
318: ADR|LV WORD
319: TREG LPTX
320: [ZMOV] [AL],[LO R]
321:
322: % PRVALUE|PEFFECT
323: WORD DXAX * DXAX AX
324: ADR|LV FS8
325: TREG LPTX
326: [ZMOVB] [AL],[LO LO R]
327: [IFV] [ZCBW]
328:
329: % PRVALUE|PEFFECT
330: WORD DXAX * DXAX AX
331: ADR|LV FU8
332: TREG LPTX
333: [ZMOVB] [AL],[LO LO R]
334: [IFV] [ZSUBB] [HI LO R],[HI LO R]
335: #endif
336:
337: /////////
338: /
339: / Do a reasonably sleazy job on field assignment. The right operand has
340: / been preshifted and masked (just like the right side of an |= or ^=
341: / operation. All you do is clear the junk and OR it in.
342: /
343: /////////
344:
345: % PEFFECT|PRVALUE
346: FS16 ANYR * * TEMP
347: ADR|LV FFLD16
348: IMM|MMX WORD
349: [ZAND] [AL],[LO CMASK]
350: [ZOR] [AL],[AR]
351: [IFV] [ZMOV] [R],[AL]
352:
353: % PEFFECT|PRVALUE
354: UWORD ANYR * * TEMP
355: ADR|LV FFLD16
356: IMM|MMX WORD
357: [ZAND] [AL],[LO CMASK]
358: [ZOR] [AL],[AR]
359: [IFV] [ZMOV] [R],[AL]
360: [IFV] [ZAND] [R],[LO EMASK]
361:
362: % PEFFECT|PRVALUE|P_SRT
363: FS16 ANYR * ANYR TEMP
364: ADR|LV FFLD16
365: TREG WORD
366: [ZAND] [AL],[LO CMASK]
367: [ZOR] [AL],[R]
368: [IFV] [ZMOV] [R],[AL]
369:
370: % PEFFECT|PRVALUE|P_SRT
371: UWORD ANYR * ANYR TEMP
372: ADR|LV FFLD16
373: TREG WORD
374: [ZAND] [AL],[LO CMASK]
375: [ZOR] [AL],[R]
376: [IFV] [ZMOV] [R],[AL]
377: [IFV] [ZAND] [R],[LO EMASK]
378:
379: % PEFFECT|PRVALUE|P_SRT
380: FS16 AX * AX TEMP
381: ADR|LV FFLD8
382: TREG WORD
383: [ZANDB] [AL],[LO CMASK]
384: [ZORB] [AL],[LO R]
385: [IFV] [ZMOVB] [LO R],[AL]
386:
387: % PEFFECT|PRVALUE|P_SRT
388: UWORD AX * AX TEMP
389: ADR|LV FFLD8
390: TREG WORD
391: [ZANDB] [AL],[LO CMASK]
392: [ZORB] [AL],[LO R]
393: [IFV] [ZMOVB] [LO R],[AL]
394: [IFV] [ZAND] [R],[LO EMASK]
395:
396: /////////
397: /
398: / Floating point. Immediate moves, and direct/direct moves
399: / are special. Otherwise we load the "fpac" and move from it.
400: / We know that the "fpac" is actually memory!!
401: /
402: / If IEEE, a runtime routine handles 32 bit float assignment.
403: / If DECVAX, we compile it inline because it is easy.
404: /
405: /////////
406:
407: #ifndef NDPDEF
408: #ifndef IEEE
409: % PEFFECT
410: FF64 AX * * NONE
411: ADR|LV FF32
412: 0|MMX *
413: [ZSUB] [R],[R]
414: [ZMOV] [HI AL],[R]
415: [ZMOV] [LO AL],[R]
416:
417: % PEFFECT
418: FF64 NONE * * NONE
419: ADR|LV FF32
420: IMM|MMX FF64
421: [ZMOV] [HI AL],[LO LO AR]
422: [ZMOV] [LO AL],[HI LO AR]
423:
424: % PEFFECT|PRVALUE|P_SRT
425: FF64 AX * FPAC FPAC
426: ADR|LV FF32
427: TREG FF64
428: % PEFFECT|PRVALUE|P_SRT
429: FF64 AX * FPAC FPAC
430: ADR|LV FF32
431: TREG FF32
432: [ZMOV] [R],[HI LO RR]
433: [ZMOV] [HI AL],[R]
434: [ZMOV] [R],[LO LO RR]
435: [ZMOV] [LO AL],[R]
436:
437: #endif
438:
439: % PEFFECT
440: FF64 AX * * NONE
441: ADR|LV FF64
442: 0|MMX *
443: [ZSUB] [R],[R]
444: [ZMOV] [HI LO AL],[R]
445: [ZMOV] [LO LO AL],[R]
446: [ZMOV] [HI HI AL],[R]
447: [ZMOV] [LO HI AL],[R]
448:
449: % PEFFECT
450: FF64 NONE * * NONE
451: ADR|LV FF64
452: IMM|MMX FF64
453: [ZMOV] [HI LO AL],[LO LO AR]
454: [ZMOV] [LO LO AL],[HI LO AR]
455: [ZMOV] [HI HI AL],[LO HI AR]
456: [ZMOV] [LO HI AL],[HI HI AR]
457:
458: % PEFFECT|PRVALUE|P_SRT
459: FF64 AX * FPAC FPAC
460: ADR|LV FF64
461: TREG FF64
462: [ZMOV] [R],[HI LO RR]
463: [ZMOV] [HI LO AL],[R]
464: [ZMOV] [R],[LO LO RR]
465: [ZMOV] [LO LO AL],[R]
466: [ZMOV] [R],[HI HI RR]
467: [ZMOV] [HI HI AL],[R]
468: [ZMOV] [R],[LO HI RR]
469: [ZMOV] [LO HI AL],[R]
470: #endif
471: #ifdef NDPDEF
472: % PEFFECT|P_SRT
473: FF64 FPAC * FPAC NONE
474: ADR|LV FF32
475: TREG FF64
476: % PEFFECT|P_SRT
477: FF64 FPAC * FPAC NONE
478: ADR|LV FF32
479: TREG FF32
480: [ZFSTPF] [AL]
481:
482: % PRVALUE|P_SRT
483: FF64 FPAC * FPAC FPAC
484: ADR|LV FF32
485: TREG FF64
486: % PRVALUE|P_SRT
487: FF64 FPAC * FPAC FPAC
488: ADR|LV FF32
489: TREG FF32
490: [ZFSTF] [AL]
491:
492: % PEFFECT|P_SRT
493: FF64 FPAC * FPAC NONE
494: ADR|LV FF64
495: TREG FF64
496: [ZFSTPD] [AL]
497:
498: % PRVALUE|P_SRT
499: FF64 FPAC * FPAC FPAC
500: ADR|LV FF64
501: TREG FF64
502: [ZFSTD] [AL]
503: #endif
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