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1.1 root 1: /////////
2: /
3: / Plain and simple assignment.
4: / Handles doubles, longs, fields, bytes and words.
5: / This table does not handle doubles.
6: / It is not clear if some kinds of double assignments should be done
7: / with move instructions to save the overhead of loading the 8087 emulator,
8: / since the emulator is big and fat.
9: / More complex double assignments, like the ones that must
10: / return a value, use the 8087.
11: / The '=' operator is a non conversion operator for pointers, words and longs.
12: / There must be some special tables here to handle the cross type cases.
13: / This approach makes everything appear to work in a rational fashion.
14: /
15: /////////
16:
17: ASSIGN:
18: % PEFFECT
19: WORD NONE * * NONE
20: REG|MMX WORD
21: 0|MMX *
22: [ZSUB] [AL],[AL]
23:
24: % PEFFECT
25: WORD NONE * * NONE
26: REG|MMX WORD
27: EASY|MMX WORD
28: % PEFFECT
29: WORD NONE * * NONE
30: ADR|LV WORD
31: REG|MMX WORD
32: % PEFFECT
33: WORD NONE * * NONE
34: ADR|LV WORD
35: IMM|MMX WORD
36: [ZMOV] [AL],[AR]
37:
38: % PEFFECT
39: WORD NONE * * NONE
40: REG|MMX WORD
41: EASY|MMX LONG
42: [ZMOV] [AL],[LO AR]
43:
44: % PEFFECT
45: WORD NONE * * NONE
46: RREG|MMX WORD
47: LEA|MMX WORD
48: [ZLEA] [AL],[NSE AR]
49:
50: % PEFFECT
51: WORD NONE * * NONE
52: ADR|LV BYTE
53: IMM|MMX WORD
54: [ZMOVB] [AL],[AR]
55:
56: % PEFFECT
57: LONG NONE * * NONE
58: ADR|LV LONG
59: IMM|MMX LONG
60: [ZMOV] [LO AL],[LO AR]
61: [ZMOV] [HI AL],[HI AR]
62:
63: % PEFFECT|PEREL|P_SRT
64: WORD ANYR * ANYR TEMP
65: ADR|LV FS8
66: TREG BYTE
67: [ZMOVB] [AL],[LO R]
68: [IFR] [ZORB] [LO R],[LO R]
69: [IFR] [REL0] [LAB]
70:
71: % PRVALUE|P_SRT
72: WORD AX * AX TEMP
73: ADR|LV FS8
74: TREG BYTE
75: [ZMOVB] [AL],[LO R]
76: [ZCBW]
77:
78: % PEFFECT|PRVALUE|PEREL|P_SRT
79: WORD ANYR * ANYR TEMP
80: ADR|LV FU8
81: TREG BYTE
82: [ZMOVB] [AL],[LO R]
83: [IFV] [ZSUBB] [HI R],[HI R]
84: [IFR] [ZORB] [LO R],[LO R]
85: [IFR] [REL0] [LAB]
86:
87: % PEFFECT|PRVALUE|PEREL
88: WORD AX * * AX
89: ADR|LV FS8
90: ADR BYTE
91: [ZMOVB] [LO R],[AR]
92: [ZMOVB] [AL],[LO R]
93: [IFV] [ZCBW]
94: [IFR] [ZORB] [LO R],[LO R]
95: [IFR] [REL0] [LAB]
96:
97: % PEFFECT|PRVALUE|PEREL
98: WORD AX * * AX
99: ADR|LV FU8
100: ADR BYTE
101: [ZMOVB] [LO R],[AR]
102: [ZMOVB] [AL],[LO R]
103: [IFV] [ZSUBB] [HI R],[HI R]
104: [IFR] [ZORB] [LO R],[LO R]
105: [IFR] [REL0] [LAB]
106:
107: % PEFFECT|PRVALUE|P_SRT
108: WORD ANYR * ANYR TEMP
109: ADR|LV WORD
110: TREG WORD
111: % PLVALUE|P_SRT
112: WORD ANYL * ANYL TEMP
113: ADR|LV WORD
114: TREG WORD
115: [ZMOV] [AL],[R]
116:
117: % PEFFECT
118: WORD AX * * NONE
119: ADR|LV WORD
120: EASY|MMX WORD
121: [ZMOV] [R],[AR]
122: [ZMOV] [AL],[R]
123:
124: % PEFFECT|PRVALUE|P_SRT
125: WORD AX * AX AX
126: ADR|LV FS8
127: TREG WORD
128: [ZMOVB] [AL],[LO R]
129: [IFV] [ZCBW]
130:
131: % PEFFECT|PRVALUE|P_SRT
132: WORD AX * AX AX
133: ADR|LV FU8
134: TREG WORD
135: [ZMOVB] [AL],[LO R]
136: [IFV] [ZSUBB] [HI R],[HI R]
137:
138: % PRVALUE|P_SRT
139: LONG ANYR * ANYR TEMP
140: ADR|LV LONG
141: TREG LONG
142: [ZMOV] [LO AL],[LO R]
143: [ZMOV] [HI AL],[HI R]
144:
145: % PEFFECT|PRVALUE
146: WORD AX * DXAX AX
147: ADR|LV WORD
148: TREG LONG
149: [ZMOV] [AL],[R]
150:
151: % PEFFECT|PRVALUE|P_SRT
152: WORD DXAX * DXAX AX
153: ADR|LV FS8
154: TREG LONG
155: [ZMOVB] [AL],[LO LO R]
156: [IFV] [ZCBW]
157:
158: % PEFFECT|PRVALUE|P_SRT
159: WORD DXAX * DXAX AX
160: ADR|LV FU8
161: TREG LONG
162: [ZMOVB] [AL],[LO LO R]
163: [IFV] [ZSUBB] [HI LO R],[HI LO R]
164:
165: /////////
166: /
167: / Assignment between pointers and integer types.
168: / These are all set up as no conversion operations in the parser.
169: / We attempt to do a reasonably good job on the common cases,
170: / like setting a pointer to NULL.
171: /
172: /////////
173:
174: #ifndef ONLYSMALL
175: % PEFFECT
176: LPTX NONE * * NONE
177: ADR|LV LPTX
178: 0|MMX *
179: [ZMOV] [LO AL],[CONST 0]
180: [ZMOV] [HI AL],[CONST 0]
181:
182: % PRVALUE
183: LPTX ANYR * * TEMP
184: ADR|LV LPTX
185: 0|MMX *
186: [ZSUB] [LO R],[LO R]
187: [ZMOV] [HI R],[LO R]
188: [ZMOV] [LO AL],[LO R]
189: [ZMOV] [HI AL],[LO R]
190:
191: % PRVALUE
192: LPTX ANYR * * TEMP
193: ADR|LV LPTX
194: ICN|MMX LPTX
195: [ZMOV] [LO R],[AR]
196: [ZSUB] [HI R],[HI R]
197: [ZMOV] [LO AL],[LO R]
198: [ZMOV] [HI AL],[HI R]
199:
200: % PLVALUE|PEFFECT
201: LPTX ANYL * * TEMP
202: ADR|LV LPTX
203: ICN|MMX LPTX
204: [ZMOV] [LO AL],[AR]
205: [ZMOV] [HI AL],[CONST 0]
206: [IFV] [ZLDES] [LO R],[AL]
207:
208: % PRVALUE
209: LPTX ANYR * * TEMP
210: ADR|LV LPTX
211: LCN|MMX LPTX
212: [ZMOV] [LO R],[LO AR]
213: [ZMOV] [HI R],[HI AR]
214: [ZMOV] [LO AL],[LO R]
215: [ZMOV] [HI AL],[HI R]
216:
217: % PLVALUE|PEFFECT
218: LPTX ANYL * * TEMP
219: ADR|LV LPTX
220: LCN|MMX LPTX
221: [ZMOV] [LO AL],[LO AR]
222: [ZMOV] [HI AL],[HI AR]
223: [IFV] [ZLDES] [LO R],[AL]
224:
225: % PRVALUE
226: LPTX ANYR * * TEMP
227: ADR|LV LPTX
228: ACS|MMX LPTX
229: [ZMOV] [LO R],[AR]
230: [ZMOV] [HI R],[REGNO CS]
231: [ZMOV] [LO AL],[LO R]
232: [ZMOV] [HI AL],[HI R]
233:
234: % PRVALUE
235: LPTX ANYR * * TEMP
236: ADR|LV LPTX
237: ADS|MMX LPTX
238: [ZMOV] [LO R],[AR]
239: [ZMOV] [HI R],[REGNO DS]
240: [ZMOV] [LO AL],[LO R]
241: [ZMOV] [HI AL],[HI R]
242:
243: % PLVALUE|PEFFECT
244: LPTX ANYL * * TEMP
245: ADR|LV LPTX
246: ACS|MMX LPTX
247: [ZMOV] [LO AL],[AR]
248: [ZMOV] [HI AL],[REGNO CS]
249: [IFV] [ZLDES] [LO R],[AL]
250:
251: % PLVALUE|PEFFECT
252: LPTX ANYL * * TEMP
253: ADR|LV LPTX
254: ADS|MMX LPTX
255: [ZMOV] [LO AL],[AR]
256: [ZMOV] [HI AL],[REGNO DS]
257: [IFV] [ZLDES] [LO R],[AL]
258:
259: % PRVALUE
260: LPTX ANYR * * TEMP
261: ADR|LV LPTX
262: DIR|MMX WORD
263: [ZMOV] [LO R],[AR]
264: [ZSUB] [HI R],[HI R]
265: [ZMOV] [LO AL],[LO R]
266: [ZMOV] [HI AL],[HI R]
267:
268: % PLVALUE|PEFFECT
269: LPTX ANYL * * TEMP
270: ADR|LV LPTX
271: DIR|MMX WORD
272: [ZMOV] [LO R],[AR]
273: [ZMOV] [LO AL],[LO R]
274: [ZMOV] [HI AL],[CONST 0]
275: [IFV] [ZLDES] [LO R],[AL]
276:
277: % PRVALUE
278: LPTX ANYR * ANYR TEMP
279: ADR|LV LPTX
280: TREG WORD
281: [ZMOV] [LO AL],[RR]
282: [ZMOV] [HI AL],[CONST 0]
283: [ZMOV] [LO R],[LO AL]
284: [ZMOV] [HI R],[HI AL]
285:
286: % PLVALUE|PEFFECT
287: LPTX ANYL * ANYR TEMP
288: ADR|LV LPTX
289: TREG WORD
290: [ZMOV] [LO AL],[RR]
291: [ZMOV] [HI AL],[CONST 0]
292: [IFV] [ZLDES] [LO R],[AL]
293:
294: % PRVALUE
295: LPTX ANYR * * TEMP
296: ADR|LV LPTX
297: DIR|MMX LONG
298: % PRVALUE
299: LONG ANYR * * TEMP
300: ADR|LV LONG
301: DIR|MMX LPTX
302: [ZMOV] [LO R],[LO AR]
303: [ZMOV] [HI R],[HI AR]
304: [ZMOV] [LO AL],[LO R]
305: [ZMOV] [HI AL],[HI R]
306:
307: % PRVALUE
308: LPTX ANYR * ANYR TEMP
309: ADR|LV LPTX
310: TREG LONG
311: [ZMOV] [LO AL],[LO RR]
312: [ZMOV] [HI AL],[HI RR]
313: [ZMOV] [LO R],[LO AL]
314: [ZMOV] [HI R],[HI AL]
315:
316: % PLVALUE|PEFFECT
317: LPTX ANYL * ANYR TEMP
318: ADR|LV LPTX
319: TREG LONG
320: [ZMOV] [LO AL],[LO RR]
321: [ZMOV] [HI AL],[HI RR]
322: [IFV] [ZLDES] [LO R],[AL]
323:
324: % PRVALUE|P_SRT
325: LPTX ANYR * ANYR TEMP
326: ADR|LV LPTX
327: TREG LPTX
328: % PLVALUE|P_SRT
329: LPTX ANYL * ANYL TEMP
330: ADR|LV LPTX
331: TREG LPTX
332: [ZMOV] [LO AL],[LO R]
333: [ZMOV] [HI AL],[HI R]
334:
335: % PRVALUE|PEFFECT|P_SRT
336: LONG ANYR * ANYR TEMP
337: ADR|LV LONG
338: TREG LPTX
339: [ZMOV] [LO AL],[LO RR]
340: [ZMOV] [HI AL],[HI RR]
341:
342: % PRVALUE|PEFFECT
343: WORD ESAX * ESAX AX
344: ADR|LV WORD
345: TREG LPTX
346: [ZMOV] [AL],[LO R]
347:
348: % PRVALUE|PEFFECT
349: WORD DXAX * DXAX AX
350: ADR|LV FS8
351: TREG LPTX
352: [ZMOVB] [AL],[LO LO R]
353: [IFV] [ZCBW]
354:
355: % PRVALUE|PEFFECT
356: WORD DXAX * DXAX AX
357: ADR|LV FU8
358: TREG LPTX
359: [ZMOVB] [AL],[LO LO R]
360: [IFV] [ZSUBB] [HI LO R],[HI LO R]
361: #endif
362:
363: /////////
364: /
365: / Do a reasonably sleazy job on field assignment.
366: / The right operand has been preshifted and masked,
367: / just like the right side of an '|=' or '^=' operation.
368: / All you do is clear the junk and OR it in.
369: /
370: /////////
371:
372: % PEFFECT|PRVALUE
373: FS16 ANYR * * TEMP
374: ADR|LV FFLD16
375: IMM|MMX WORD
376: [ZAND] [AL],[LO CMASK]
377: [ZOR] [AL],[AR]
378: [IFV] [ZMOV] [R],[AL]
379:
380: % PEFFECT|PRVALUE
381: UWORD ANYR * * TEMP
382: ADR|LV FFLD16
383: IMM|MMX WORD
384: [ZAND] [AL],[LO CMASK]
385: [ZOR] [AL],[AR]
386: [IFV] [ZMOV] [R],[AL]
387: [IFV] [ZAND] [R],[LO EMASK]
388:
389: % PEFFECT|PRVALUE|P_SRT
390: FS16 ANYR * ANYR TEMP
391: ADR|LV FFLD16
392: TREG WORD
393: [ZAND] [AL],[LO CMASK]
394: [ZOR] [AL],[R]
395: [IFV] [ZMOV] [R],[AL]
396:
397: % PEFFECT|PRVALUE|P_SRT
398: UWORD ANYR * ANYR TEMP
399: ADR|LV FFLD16
400: TREG WORD
401: [ZAND] [AL],[LO CMASK]
402: [ZOR] [AL],[R]
403: [IFV] [ZMOV] [R],[AL]
404: [IFV] [ZAND] [R],[LO EMASK]
405:
406: % PEFFECT|PRVALUE|P_SRT
407: FS16 AX * AX TEMP
408: ADR|LV FFLD8
409: TREG WORD
410: [ZANDB] [AL],[LO CMASK]
411: [ZORB] [AL],[LO R]
412: [IFV] [ZMOVB] [LO R],[AL]
413:
414: % PEFFECT|PRVALUE|P_SRT
415: UWORD AX * AX TEMP
416: ADR|LV FFLD8
417: TREG WORD
418: [ZANDB] [AL],[LO CMASK]
419: [ZORB] [AL],[LO R]
420: [IFV] [ZMOVB] [LO R],[AL]
421: [IFV] [ZAND] [R],[LO EMASK]
422:
423: /////////
424: /
425: / Floating point.
426: / Immediate moves and direct/direct moves are special.
427: / Otherwise, load the "fpac" and move from it.
428: / We know that the "fpac" is actually memory!!
429: /
430: / If IEEE, a runtime routine handles 32 bit float assignment.
431: / If DECVAX, we compile it inline because it is easy.
432: /
433: /////////
434:
435: #ifndef NDPDEF
436: #ifndef IEEE
437: % PEFFECT
438: FF64 AX * * NONE
439: ADR|LV FF32
440: 0|MMX *
441: [ZSUB] [R],[R]
442: [ZMOV] [HI AL],[R]
443: [ZMOV] [LO AL],[R]
444:
445: % PEFFECT
446: FF64 NONE * * NONE
447: ADR|LV FF32
448: IMM|MMX FF64
449: [ZMOV] [HI AL],[LO LO AR]
450: [ZMOV] [LO AL],[HI LO AR]
451:
452: % PEFFECT|PRVALUE|P_SRT
453: FF64 AX * FPAC FPAC
454: ADR|LV FF32
455: TREG FF64
456: % PEFFECT|PRVALUE|P_SRT
457: FF64 AX * FPAC FPAC
458: ADR|LV FF32
459: TREG FF32
460: [ZMOV] [R],[HI LO RR]
461: [ZMOV] [HI AL],[R]
462: [ZMOV] [R],[LO LO RR]
463: [ZMOV] [LO AL],[R]
464:
465: #endif
466:
467: % PEFFECT
468: FF64 AX * * NONE
469: ADR|LV FF64
470: 0|MMX *
471: [ZSUB] [R],[R]
472: [ZMOV] [HI LO AL],[R]
473: [ZMOV] [LO LO AL],[R]
474: [ZMOV] [HI HI AL],[R]
475: [ZMOV] [LO HI AL],[R]
476:
477: % PEFFECT
478: FF64 NONE * * NONE
479: ADR|LV FF64
480: IMM|MMX FF64
481: [ZMOV] [HI LO AL],[LO LO AR]
482: [ZMOV] [LO LO AL],[HI LO AR]
483: [ZMOV] [HI HI AL],[LO HI AR]
484: [ZMOV] [LO HI AL],[HI HI AR]
485:
486: % PEFFECT|PRVALUE|P_SRT
487: FF64 AX * FPAC FPAC
488: ADR|LV FF64
489: TREG FF64
490: [ZMOV] [R],[HI LO RR]
491: [ZMOV] [HI LO AL],[R]
492: [ZMOV] [R],[LO LO RR]
493: [ZMOV] [LO LO AL],[R]
494: [ZMOV] [R],[HI HI RR]
495: [ZMOV] [HI HI AL],[R]
496: [ZMOV] [R],[LO HI RR]
497: [ZMOV] [LO HI AL],[R]
498: #endif
499: #ifdef NDPDEF
500: % PEFFECT|P_SRT
501: FF64 FPAC * FPAC NONE
502: ADR|LV FF32
503: TREG FF64
504: % PEFFECT|P_SRT
505: FF64 FPAC * FPAC NONE
506: ADR|LV FF32
507: TREG FF32
508: [ZFSTPF] [AL]
509:
510: % PRVALUE|P_SRT
511: FF64 FPAC * FPAC FPAC
512: ADR|LV FF32
513: TREG FF64
514: % PRVALUE|P_SRT
515: FF64 FPAC * FPAC FPAC
516: ADR|LV FF32
517: TREG FF32
518: [ZFSTF] [AL]
519:
520: % PEFFECT|P_SRT
521: FF64 FPAC * FPAC NONE
522: ADR|LV FF64
523: TREG FF64
524: [ZFSTPD] [AL]
525:
526: % PRVALUE|P_SRT
527: FF64 FPAC * FPAC FPAC
528: ADR|LV FF64
529: TREG FF64
530: [ZFSTD] [AL]
531: #endif
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