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1.1 root 1: /////////
2: /
3: / Assigned subtract.
4: /
5: /////////
6:
7: ASUB:
8: % PEFFECT|PRVALUE|PREL
9: WORD ANYR * * TEMP
10: ADR|LV WORD
11: 1|MMX *
12: % PLVALUE
13: WORD ANYL * * TEMP
14: ADR|LV WORD
15: 1|MMX *
16: [ZDEC] [AL]
17: [IFV] [ZMOV] [R],[AL]
18: [IFR] [REL0] [LAB]
19:
20: % PEFFECT|PRVALUE|PREL
21: WORD AX * * AX
22: ADR|LV FS8
23: 1|MMX *
24: [ZDECB] [AL]
25: [IFV] [ZMOVB] [LO R],[AL]
26: [IFV] [ZCBW]
27: [IFR] [REL0] [LAB]
28:
29: % PEFFECT|PRVALUE|PREL
30: WORD AX * * AX
31: ADR|LV FU8
32: 1|MMX *
33: [ZDECB] [AL]
34: [IFV] [ZMOVB] [LO R],[AL]
35: [IFV] [ZSUBB] [HI R],[HI R]
36: [IFR] [REL0] [LAB]
37:
38: #ifndef ONLYSMALL
39: % PRVALUE
40: LPTX ANYR * * TEMP
41: ADR|LV LPTX
42: 1|MMX *
43: [ZDEC] [AL]
44: [ZMOV] [LO R],[LO AL]
45: [ZMOV] [HI R],[HI AL]
46:
47: % PLVALUE|PEFFECT
48: LPTX ANYL * * TEMP
49: ADR|LV LPTX
50: 1|MMX *
51: [ZDEC] [AL]
52: [IFV] [ZLDES] [LO R],[AL]
53: #endif
54:
55: % PEFFECT|PRVALUE|PREL
56: WORD ANYR * * TEMP
57: REG|MMX WORD
58: ADR|IMM WORD
59: % PLVALUE
60: WORD ANYL * * TEMP
61: REG|MMX WORD
62: ADR|IMM WORD
63: [ZSUB] [AL],[AR]
64: [IFV] [ZMOV] [R],[AL]
65: [IFR] [REL0] [LAB]
66:
67: % PEFFECT|PRVALUE|PREL
68: WORD ANYR * * TEMP
69: ADR|LV WORD
70: IMM|MMX WORD
71: % PEFFECT|PRVALUE|PREL
72: WORD ANYR * * TEMP
73: ADR|LV WORD
74: REG|MMX WORD
75: % PLVALUE
76: WORD ANYL * * TEMP
77: ADR|LV WORD
78: IMM|MMX WORD
79: % PLVALUE
80: WORD ANYL * * TEMP
81: ADR|LV WORD
82: REG|MMX WORD
83: [ZSUB] [AL],[AR]
84: [IFV] [ZMOV] [R],[AL]
85: [IFR] [REL0] [LAB]
86:
87: % PEFFECT|PRVALUE|PREL
88: WORD AX * * AX
89: ADR|LV FS8
90: IMM|MMX WORD
91: [ZSUBB] [AL],[AR]
92: [IFV] [ZMOVB] [LO R],[AL]
93: [IFV] [ZCBW]
94: [IFR] [REL0] [LAB]
95:
96: % PEFFECT|PRVALUE|PREL
97: WORD AX * * AX
98: ADR|LV FU8
99: IMM|MMX WORD
100: [ZSUBB] [AL],[AR]
101: [IFV] [ZMOVB] [LO R],[AL]
102: [IFV] [ZSUBB] [HI R],[HI R]
103: [IFR] [REL0] [LAB]
104:
105: #ifndef ONLYSMALL
106: % PRVALUE
107: LPTX ANYR * * TEMP
108: ADR|LV LPTX
109: IMM|MMX WORD
110: [ZSUB] [AL],[AR]
111: [ZMOV] [LO R],[LO AL]
112: [ZMOV] [HI R],[HI AL]
113:
114: % PLVALUE|PEFFECT
115: LPTX ANYL * * TEMP
116: ADR|LV LPTX
117: IMM|MMX WORD
118: [ZSUB] [AL],[AR]
119: [IFV] [ZLDES] [LO R],[AL]
120: #endif
121:
122: % PEFFECT|PRVALUE|PLT|PGE
123: LONG DXAX * * DXAX
124: ADR|LV LONG
125: LHC|MMX LONG
126: [ZSUB] [HI AL],[HI AR]
127: [IFV] [ZMOV] [LO R],[LO AL]
128: [IFV] [ZMOV] [HI R],[HI AL]
129: [IFR] [REL1] [LAB]
130:
131: % PEFFECT|PRVALUE|PLT|PGE
132: LONG DXAX * * DXAX
133: ADR|LV LONG
134: IMM|MMX LONG
135: [ZSUB] [LO AL],[LO AR]
136: [ZSBB] [HI AL],[HI AR]
137: [IFV] [ZMOV] [LO R],[LO AL]
138: [IFV] [ZMOV] [HI R],[HI AL]
139: [IFR] [REL1] [LAB]
140:
141: % PEFFECT|PRVALUE|PREL|P_SRT
142: WORD ANYR * ANYR TEMP
143: ADR|LV WORD
144: TREG WORD
145: % PLVALUE|P_SRT
146: WORD ANYL * ANYL TEMP
147: ADR|LV WORD
148: TREG WORD
149: [ZSUB] [AL],[R]
150: [IFV] [ZMOV] [R],[AL]
151: [IFR] [REL0] [LAB]
152:
153: % PEFFECT|PRVALUE|PREL|P_SRT
154: WORD AX * AX AX
155: ADR|LV FS8
156: TREG WORD
157: [ZSUBB] [AL],[LO R]
158: [IFV] [ZMOVB] [LO R],[AL]
159: [IFV] [ZCBW]
160: [IFR] [REL0] [LAB]
161:
162: % PEFFECT|PRVALUE|PREL|P_SRT
163: WORD AX AX * AX
164: ADR|LV FU8
165: TREG WORD
166: [ZSUBB] [AL],[LO R]
167: [IFV] [ZMOVB] [LO R],[AL]
168: [IFV] [ZSUBB] [HI R],[HI R]
169: [IFR] [REL0] [LAB]
170:
171: #ifndef ONLYSMALL
172: % PRVALUE
173: LPTX ANYR * ANYR TEMP
174: ADR|LV LPTX
175: TREG WORD
176: [ZSUB] [AL],[RR]
177: [ZMOV] [LO R],[LO AL]
178: [ZMOV] [HI R],[HI AL]
179:
180: % PLVALUE|PEFFECT
181: LPTX ANYL * ANYR TEMP
182: ADR|LV LPTX
183: TREG WORD
184: [ZSUB] [AL],[RR]
185: [IFV] [ZLDES] [LO R],[AL]
186: #endif
187:
188: % PRVALUE|PREL
189: WORD ANYR * * TEMP
190: ADR|LV WORD
191: ADR|IMM WORD
192: % PLVALUE
193: WORD ANYL * * TEMP
194: ADR|LV WORD
195: ADR|IMM WORD
196: [ZMOV] [R],[AL]
197: [ZSUB] [R],[AR]
198: [ZMOV] [AL],[R]
199: [IFR] [REL0] [LAB]
200:
201: % PRVALUE|PREL
202: WORD AX * * AX
203: ADR|LV FS8
204: ADR|IMM WORD
205: [ZMOVB] [LO R],[AL]
206: [ZCBW]
207: [ZSUB] [R],[AR]
208: [ZMOVB] [AL],[LO R]
209: [IFR] [REL0] [LAB]
210:
211: % PRVALUE|PREL
212: WORD AX * * AX
213: ADR|LV FU8
214: ADR|IMM WORD
215: [ZMOVB] [LO R],[AL]
216: [ZSUBB] [HI R],[HI R]
217: [ZSUB] [R],[AR]
218: [ZMOVB] [AL],[LO R]
219: [IFR] [REL0] [LAB]
220:
221: % PEFFECT
222: LONG DXAX * * NONE
223: ADR|LV LONG
224: DIR|MMX FS16
225: [ZMOV] [LO R],[AR]
226: [ZCWD]
227: [ZSUB] [LO AL],[LO R]
228: [ZSBB] [HI AL],[HI R]
229:
230: % PEFFECT
231: LONG DXAX * * NONE
232: ADR|LV LONG
233: DIR|MMX FU16
234: [ZMOV] [LO R],[AR]
235: [ZSUB] [HI R],[HI R]
236: [ZSUB] [LO AL],[LO R]
237: [ZSBB] [HI AL],[HI R]
238:
239: % PEFFECT
240: LONG DXAX * DXAX NONE
241: ADR|LV LONG
242: TREG LONG
243: [ZSUB] [LO AL],[LO R]
244: [ZSBB] [HI AL],[HI R]
245:
246: % PRVALUE|PLT|PGE|P_SRT
247: LONG DXAX * DXAX DXAX
248: ADR|LV LONG
249: TREG LONG
250: [ZSUB] [LO AL],[LO R]
251: [ZSBB] [HI AL],[HI R]
252: [ZMOV] [LO R],[LO AL]
253: [ZMOV] [HI R],[HI AL]
254: [IFR] [REL1] [LAB]
255:
256: % PRVALUE|PLT|PGE
257: LONG DXAX * * DXAX
258: ADR|LV LONG
259: ADR|IMM LONG
260: [ZMOV] [LO R],[LO AL]
261: [ZMOV] [HI R],[HI AL]
262: [ZSUB] [LO R],[LO AR]
263: [ZSBB] [HI R],[HI AR]
264: [ZMOV] [LO AL],[LO R]
265: [ZMOV] [HI AL],[HI R]
266: [IFR] [REL1] [LAB]
267:
268: /////////
269: /
270: / The left hand operand is an lvalue bit field.
271: / The right operand has been preshifted to the appropriate place.
272: / If the value is required, there is a shift on top of the '+='
273: / or '-=' node. Grab the machine object that holds the field,
274: / add or subtract the right operand from it (which performs the
275: / computation in the field, then extract the result and replace
276: / the value in the machine object.
277: /
278: /////////
279:
280: % PRVALUE
281: WORD AX * * AX
282: ADR|LV FFLD8
283: ADR|IMM WORD
284: [ZMOVB] [LO R],[AL]
285: [ZCBW]
286: [ZSUB] [R],[AR]
287: [ZAND] [R],[LO EMASK]
288: [ZANDB] [AL],[LO CMASK]
289: [ZORB] [AL],[R]
290:
291: % PRVALUE
292: WORD ANYR * * TEMP
293: ADR|LV FFLD16
294: ADR|IMM WORD
295: [ZMOV] [R],[AL]
296: [ZSUB] [R],[AR]
297: [ZAND] [R],[LO EMASK]
298: [ZAND] [AL],[LO CMASK]
299: [ZOR] [AL],[R]
300:
301: ////////
302: /
303: / Floating point, using the numeric
304: / data coprocessor (8087).
305: /
306: ////////
307:
308: #ifdef NDPDEF
309: % PEFFECT|PRVALUE
310: FF32|FF64 FPAC * FPAC FPAC
311: ADR|LV FF32
312: TREG FF64
313: [ZFRSUBF] [AL]
314: [IFV] [ZFSTF] [AL]
315: [IFE] [ZFSTPF] [AL]
316:
317: % PEFFECT|PRVALUE
318: FF32|FF64 FPAC * FPAC FPAC
319: ADR|LV FF64
320: TREG FF64
321: [ZFRSUBD] [AL]
322: [IFV] [ZFSTD] [AL]
323: [IFE] [ZFSTPD] [AL]
324: #endif
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