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1.1 root 1: /////////
2: /
3: / Leaf nodes, fixups, type conversions and casts.
4: / All performed by a single table.
5: / These tables MUST be correct and complete, since they get used
6: / to fix up any missing entries in the other tables.
7: / Work on them carefully!
8: / The compiler is not very good at detecting errors or ommissions here.
9: / A missing fixup table usually makes the compiler run out of stack
10: / as the code generator calls itself again and again.
11: /
12: /////////
13:
14: CONVERT:
15: CAST:
16: FIXUP:
17: LEAF:
18:
19: /////////
20: /
21: / Load a constant 0.
22: / The subtract instruction is the shortest and fastest way to zero a register.
23: / The SUB then MOV sequence is used to zero a long register
24: / (instead of SUB then SUB) so that the same code table entry
25: / can be used to zero a segment register/index register pair.
26: /
27: /////////
28:
29: % PRVALUE
30: WORD ANYR * * TEMP
31: 0|MMX *
32: * *
33: % PLVALUE
34: WORD ANYL * * TEMP
35: 0|MMX *
36: * *
37: [ZSUB] [R],[R]
38:
39: % PRVALUE
40: LONG|LPTX ANYR * * TEMP
41: 0|MMX *
42: * *
43: #ifndef ONLYSMALL
44: % PLVALUE
45: LPTX ANYL * * TEMP
46: 0|MMX *
47: * *
48: #endif
49: [ZSUB] [LO R],[LO R]
50: [ZMOV] [HI R],[LO R]
51:
52: /////////
53: /
54: / The constants 0.0 and 1.0 have special instructions
55: / to make pushing them onto the 8087 stack easier.
56: / There are other constant instructions too (push PI, etc.)
57: / but we make absolutely no attempt to use them.
58: /
59: /////////
60:
61: #ifdef NDPDEF
62: % PRVALUE
63: FF64 FPAC * * FPAC
64: 0|MMX *
65: * *
66: [ZFLDZ]
67:
68: % PRVALUE
69: FF64 FPAC * * FPAC
70: 1|MMX *
71: * *
72: [ZFLD1]
73: #endif
74:
75: /////////
76: /
77: / Long constants of the form ....0000 and 0000.... can have
78: / the 0000 half loaded with a SUB, saving one byte.
79: /
80: /////////
81:
82: % PRVALUE
83: LONG ANYR * * TEMP
84: UHC|MMX LONG
85: * *
86: [ZMOV] [LO R],[LO AL]
87: [ZSUB] [HI R],[HI R]
88:
89: % PRVALUE
90: LONG ANYR * * TEMP
91: LHC|MMX LONG
92: * *
93: [ZSUB] [LO R],[LO R]
94: [ZMOV] [HI R],[HI AL]
95:
96: /////////
97: /
98: / Load simple lvalues.
99: / The strange BYTE table is for loading the elements of small enumerations,
100: / which have the type BYTE.
101: /
102: /////////
103:
104: % PRVALUE
105: WORD ANYR * * TEMP
106: LEA|MMX WORD
107: * *
108: % PLVALUE
109: WORD ANYL * * TEMP
110: LEA|MMX WORD
111: * *
112: [ZLEA] [R],[NSE AL]
113:
114: % PRVALUE
115: WORD|BYTE ANYR * * TEMP
116: IMM|MMX BYTE
117: * *
118: % PRVALUE
119: WORD ANYR * * TEMP
120: ADR|IMM WORD
121: * *
122: % PLVALUE
123: WORD ANYL * * TEMP
124: ADR|IMM WORD
125: * *
126: [ZMOV] [R],[AL]
127:
128: % PRVALUE
129: LONG ANYR * * TEMP
130: ADR|IMM LONG
131: * *
132: % PLVALUE
133: LONG ANYL * * TEMP
134: ADR|IMM LONG
135: * *
136: [ZMOV] [LO R],[LO AL]
137: [ZMOV] [HI R],[HI AL]
138: #ifdef NDPDEF
139: % PRVALUE
140: FF64 FPAC * * FPAC
141: ADR FF64
142: * *
143: [ZFLDD] [AL]
144: #endif
145:
146: /////////
147: /
148: / LARGE model pointers.
149: / Many cases have to be broken out,
150: / because most of the time the appropriate segment register is only implied.
151: / It gets passed in the flags.
152: /
153: /////////
154:
155: #ifndef ONLYSMALL
156: % PRVALUE
157: LPTX ANYR * * TEMP
158: LSS|MMX LPTX
159: * *
160: % PLVALUE
161: LPTX ANYL * * TEMP
162: LSS|MMX LPTX
163: * *
164: [ZLEA] [LO R],[NSE AL]
165: [ZPUSH] [REGNO SS]
166: [ZPOP] [HI R]
167:
168: % PRVALUE
169: LPTX ANYR * * TEMP
170: RREG|LREG|MMX LPTX
171: * *
172: % PLVALUE
173: LPTX ANYL * * TEMP
174: RREG|MMX LPTX
175: * *
176: [ZMOV] [LO R],[LO AL]
177: [ZMOV] [HI R],[HI AL]
178:
179: % PRVALUE
180: LPTX ANYR * * TEMP
181: SREG|MMX LPTX
182: * *
183: % PLVALUE
184: LPTX ANYL * * TEMP
185: LREG|SREG|MMX LPTX
186: * *
187: [ZMOV] [LO R],[LO AL]
188: [ZPUSH] [HI AL]
189: [ZPOP] [HI R]
190:
191: % PRVALUE
192: LPTX ANYR * * TEMP
193: ICN|MMX LPTX
194: * *
195: [ZMOV] [LO R],[AL]
196: [ZSUB] [HI R],[HI R]
197:
198: % PLVALUE
199: LPTX ANYL * * TEMP
200: ICN|MMX LPTX
201: * *
202: [ZSUB] [LO R],[LO R]
203: [ZMOV] [HI R],[LO R]
204: [ZMOV] [LO R],[AL]
205:
206: % PRVALUE
207: LPTX ANYR * * TEMP
208: LCN|MMX LPTX
209: * *
210: [ZMOV] [LO R],[LO AL]
211: [ZMOV] [HI R],[HI AL]
212:
213: % PLVALUE
214: LPTX ANYL * * TEMP
215: LCN|MMX LPTX
216: * *
217: [ZMOV] [LO R],[HI AL]
218: [ZMOV] [HI R],[LO R]
219: [ZMOV] [LO R],[LO AL]
220:
221: % PRVALUE
222: LPTX ANYR * * TEMP
223: ACS|MMX LPTX
224: * *
225: % PLVALUE
226: LPTX ANYL * * TEMP
227: ACS|MMX LPTX
228: * *
229: [ZMOV] [LO R],[AL]
230: [ZPUSH] [REGNO CS]
231: [ZPOP] [HI R]
232:
233: % PRVALUE
234: LPTX ANYR * * TEMP
235: ADS|MMX LPTX
236: * *
237: % PLVALUE
238: LPTX ANYL * * TEMP
239: ADS|MMX LPTX
240: * *
241: [ZMOV] [LO R],[AL]
242: [ZPUSH] [REGNO DS]
243: [ZPOP] [HI R]
244:
245: % PRVALUE
246: LPTX ANYR * * TEMP
247: ADR LPTX
248: * *
249: [ZMOV] [LO R],[LO AL]
250: [ZMOV] [HI R],[HI AL]
251:
252: % PLVALUE
253: LPTX ANYL * * TEMP
254: ADR LPTX
255: * *
256: [ZLDES] [LO R],[AL]
257: #endif
258:
259: /////////
260: /
261: / The FF32 load actually loads 64 bits.
262: / It is just like the S8 and U8 loads, and exists for much the same reasons.
263: /
264: /////////
265:
266: #ifndef NDPDEF
267: % PRVALUE
268: FF32|FF64 FPAC AX * FPAC
269: ADR FF32
270: * *
271: [ZMOV] [REGNO AX],[HI AL]
272: [ZMOV] [HI LO R],[REGNO AX]
273: [ZMOV] [REGNO AX],[LO AL]
274: [ZMOV] [LO LO R],[REGNO AX]
275: [ZMOV] [HI HI R],[CONST 0]
276: [ZMOV] [LO HI R],[CONST 0]
277:
278: % PRVALUE
279: FF64 FPAC * * FPAC
280: IMM|MMX FF64
281: * *
282: [ZMOV] [HI LO R],[LO LO AL]
283: [ZMOV] [LO LO R],[HI LO AL]
284: [ZMOV] [HI HI R],[LO HI AL]
285: [ZMOV] [LO HI R],[HI HI AL]
286:
287: % PRVALUE
288: FF64 FPAC AX * FPAC
289: ADR FF64
290: * *
291: [ZMOV] [REGNO AX],[HI LO AL]
292: [ZMOV] [HI LO R],[REGNO AX]
293: [ZMOV] [REGNO AX],[LO LO AL]
294: [ZMOV] [LO LO R],[REGNO AX]
295: [ZMOV] [REGNO AX],[HI HI AL]
296: [ZMOV] [HI HI R],[REGNO AX]
297: [ZMOV] [REGNO AX],[LO HI AL]
298: [ZMOV] [LO HI R],[REGNO AX]
299: #endif
300:
301: /////////
302: /
303: / Widen conversions.
304: /
305: /////////
306:
307: / Widen to word.
308: % PRVALUE
309: WORD AX * * TEMP
310: RREG|MMX BYTE
311: * *
312: [ZMOV] [R],[AL]
313: [ZCBW]
314:
315: % PRVALUE|PEFFECT
316: WORD|FS8 AX * * TEMP
317: ADR|IMM FS8
318: * *
319: [ZMOVB] [LO R],[AL]
320: [IFV] [ZCBW]
321:
322: % PRVALUE|PEFFECT
323: WORD|FU8 AX * * TEMP
324: ADR|IMM FU8
325: * *
326: [ZMOVB] [LO R],[AL]
327: [IFV] [ZSUBB] [HI R],[HI R]
328:
329: % PRVALUE|P_SLT
330: WORD ANYR ANYR * TEMP
331: TREG BYTE
332: * *
333: ;
334:
335: / Widen to long.
336: % PRVALUE
337: LONG DXAX * * TEMP
338: RREG|MMX BYTE
339: * *
340: [ZMOV] [LO R],[AL]
341: [ZCWD]
342:
343: % PRVALUE|P_SLT
344: LONG DXAX AX * TEMP
345: TREG BYTE
346: * *
347: [ZCWD]
348:
349: % PRVALUE
350: LONG DXAX * * TEMP
351: ADR FS8
352: * *
353: [ZMOVB] [LO LO R],[AL]
354: [ZCBW]
355: [ZCWD]
356:
357: % PRVALUE
358: LONG DXAX * * TEMP
359: ADR FU8
360: * *
361: [ZMOVB] [LO LO R],[AL]
362: [ZSUBB] [HI LO R],[HI LO R]
363: [ZCWD]
364:
365: % PRVALUE
366: LONG DXAX * * TEMP
367: ADR|IMM FS16
368: * *
369: [ZMOV] [LO R],[AL]
370: [ZCWD]
371:
372: % PRVALUE
373: LONG DXAX * * TEMP
374: ADR|IMM UWORD
375: * *
376: [ZMOV] [LO R],[AL]
377: [ZSUB] [HI R],[HI R]
378:
379: #ifdef NDPDEF
380: / Widen to float.
381: % PRVALUE
382: FF32|FF64 FPAC * * FPAC
383: ADR FS16
384: * *
385: [ZFLDI] [AL]
386:
387: % PRVALUE
388: FF32|FF64 FPAC * * FPAC
389: ADR FS32
390: * *
391: [ZFLDL] [AL]
392:
393: % PRVALUE
394: FF32|FF64 FPAC * * FPAC
395: ADR FF32
396: * *
397: [ZFLDF] [AL]
398: #endif
399:
400: /////////
401: /
402: / Conversions to and from LARGE model pointers.
403: /
404: /////////
405:
406: #ifndef ONLYSMALL
407:
408: / Byte to LARGE pointer.
409: % PRVALUE
410: LPTX DXAX * * DXAX
411: ADR|IMM FS8
412: * *
413: [ZSUB] [HI R],[HI R]
414: [ZMOVB] [LO LO R],[AL]
415: [ZCBW]
416:
417: % PLVALUE
418: LPTX ESAX * * ESAX
419: ADR|IMM FS8
420: * *
421: [ZSUB] [LO R],[LO R] / ES = 0
422: [ZMOV] [HI R],[LO R]
423: [ZMOVB] [LO LO R],[AL]
424: [ZCBW]
425:
426: % PRVALUE
427: LPTX DXAX * * DXAX
428: ADR|IMM FU8
429: * *
430: [ZSUB] [HI R],[HI R]
431: [ZMOVB] [LO LO R],[AL]
432: [ZSUBB] [HI LO R],[HI LO R]
433:
434: % PLVALUE
435: LPTX ESAX * * ESAX
436: ADR|IMM FU8
437: * *
438: [ZSUB] [LO R],[LO R] / ES = 0
439: [ZMOV] [HI R],[LO R]
440: [ZMOVB] [LO LO R],[AL] / AH already 0
441:
442: / Word to LARGE pointer.
443: % PRVALUE
444: LPTX ANYR * * TEMP
445: ADR|IMM WORD
446: * *
447: [ZSUB] [HI R],[HI R]
448: [ZMOV] [LO R],[AL]
449:
450: % PLVALUE
451: LPTX ANYL * * TEMP
452: ADR|IMM WORD
453: * *
454: [ZSUB] [LO R],[LO R] / ES = 0
455: [ZMOV] [HI R],[LO R]
456: [ZMOV] [LO R],[AL]
457:
458: / Long to LARGE pointer.
459: % PRVALUE
460: LPTX ANYR * * TEMP
461: IMM|MMX LONG
462: * *
463: [ZMOV] [HI R],[HI AL]
464: [ZMOV] [LO R],[LO AL]
465:
466: % PRVALUE
467: LPTX ANYR DXAX * TEMP
468: TREG LONG
469: * *
470: % PLVALUE
471: LPTX ANYL DXAX * TEMP
472: TREG LONG
473: * *
474: [ZMOV] [HI R],[HI RL]
475: [ZMOV] [LO R],[LO RL]
476:
477: % PRVALUE
478: LPTX ANYR * * TEMP
479: ADR LONG
480: * *
481: % PLVALUE
482: LPTX ANYL * * TEMP
483: ADR LONG
484: * *
485: [ZMOV] [HI R],[HI AL]
486: [ZMOV] [LO R],[LO AL]
487:
488: / LARGE pointer to long.
489: % PRVALUE
490: LONG ANYR * * TEMP
491: LSS|MMX LPTX
492: * *
493: [ZMOV] [HI R],[REGNO SS]
494: [ZLEA] [LO R],[NSE AL]
495:
496: % PRVALUE
497: LONG ANYR * * TEMP
498: ICN|MMX LPTX
499: * *
500: [ZSUB] [HI R],[HI R]
501: [ZMOV] [LO R],[AL]
502:
503: % PRVALUE
504: LONG ANYR * * TEMP
505: LCN|MMX LPTX
506: * *
507: [ZMOV] [HI R],[HI AL]
508: [ZMOV] [LO R],[LO AL]
509:
510: % PRVALUE
511: LONG ANYR * * TEMP
512: ADS|MMX LPTX
513: * *
514: [ZMOV] [HI R],[REGNO DS]
515: [ZMOV] [LO R],[AL]
516:
517: % PRVALUE
518: LONG ANYR * * TEMP
519: ADR LPTX
520: * *
521: [ZMOV] [HI R],[HI AL]
522: [ZMOV] [LO R],[LO AL]
523: #endif
524:
525: /////////
526: /
527: / Shrinks.
528: / Two kinds.
529: / The first kind (long => int) just grabs the correct bit.
530: / The other kind (int => char) performs a range reduction.
531: /
532: /////////
533:
534: / Long to word.
535: % PRVALUE
536: WORD ANYR * * TEMP
537: IMM|MMX LONG|LPTX
538: * *
539: [ZMOV] [R],[LO AL]
540:
541: % PRVALUE|P_SLT
542: WORD DXAX DXAX * AX
543: TREG LONG|LPTX
544: * *
545: ;
546:
547: % PRVALUE
548: WORD ANYR * * TEMP
549: ADR LONG|LPTX
550: * *
551: [ZMOV] [R],[LO AL]
552:
553: / Long to byte.
554: % PRVALUE
555: FS8 AX * * TEMP
556: RREG|MMX LONG|LPTX
557: * *
558: [ZMOV] [R],[LO AL]
559: [ZCBW]
560:
561: % PRVALUE
562: FU8 AX * * TEMP
563: RREG|MMX LONG|LPTX
564: * *
565: [ZMOV] [R],[LO AL]
566: [ZSUBB] [HI R],[HI R]
567:
568: % PRVALUE
569: FS8 AX * * TEMP
570: ADR|IMM LONG|LPTX
571: * *
572: [ZMOV] [R],[LO AL]
573: [ZCBW]
574:
575: % PRVALUE
576: FU8 AX * * TEMP
577: ADR|IMM LONG|LPTX
578: * *
579: [ZMOV] [R],[LO AL]
580: [ZSUBB] [HI R],[HI R]
581:
582: % PRVALUE
583: FS8 DXAX DXAX * AX
584: TREG LONG|LPTX
585: * *
586: [ZCBW]
587:
588: % PRVALUE
589: FU8 DXAX DXAX * AX
590: TREG LONG|LPTX
591: * *
592: ;
593:
594: / Word to byte.
595: % PRVALUE
596: FS8 AX * * TEMP
597: RREG|MMX WORD
598: * *
599: [ZMOV] [R],[AL]
600: [ZCBW]
601:
602: % PRVALUE
603: FU8 AX * * TEMP
604: RREG|MMX WORD
605: * *
606: [ZMOV] [R],[AL]
607: [ZSUBB] [HI R],[HI R]
608:
609: % PRVALUE
610: FS8 AX * * TEMP
611: ADR|IMM WORD
612: * *
613: [ZMOVB] [LO R],[HI AL]
614: [ZCBW]
615:
616: % PRVALUE
617: FU8 AX * * TEMP
618: ADR|IMM WORD
619: * *
620: [ZMOVB] [LO R],[HI AL]
621: [ZSUBB] [HI R],[HI R]
622:
623: % PRVALUE|P_SLT
624: FS8 AX AX * TEMP
625: TREG WORD
626: * *
627: [ZCBW]
628:
629: % PRVALUE|P_SLT
630: FU8 AX AX * TEMP
631: TREG WORD
632: * *
633: [ZSUBB] [HI R],[HI R]
634:
635: /////////
636: /
637: / Test contexts.
638: / These handle checking of leaf nodes.
639: / They also are responsible for transforming the result of a PRVALUE match
640: / into a match that generates a jump.
641: / Pointers are a little bit special.
642: / If the relation is EQ or NE, look at the entire pointer.
643: / If it is something else, only look at the offset part.
644: /
645: /////////
646:
647: % PSREL
648: WORD NONE * * NONE
649: RREG|MMX WORD
650: * *
651: [ZOR] [AL],[AL]
652: [REL0] [LAB]
653:
654: % PSREL
655: WORD AX * * NONE
656: ADR WORD
657: * *
658: [ZCMP] [AL],[CONST 0]
659: [REL0] [LAB]
660:
661: % PSREL
662: WORD|BYTE AX * * NONE
663: ADR BYTE
664: * *
665: [ZCMPB] [AL],[CONST 0]
666: [REL0] [LAB]
667:
668: % PEREL
669: LONG NONE * * NONE
670: RREG|MMX LONG
671: * *
672: [ZOR] [LO AL],[HI AL]
673: [REL0] [LAB]
674:
675: % PEREL
676: LONG AX * * NONE
677: ADR|IMM LONG
678: * *
679: [ZMOV] [R],[LO AL]
680: [ZOR] [R],[HI AL]
681: [REL0] [LAB]
682:
683: % PLT|PGE
684: LONG NONE * * NONE
685: RREG|MMX LONG
686: * *
687: [ZOR] [HI AL],[HI AL]
688: [REL1] [LAB]
689:
690: % PLT|PGE
691: LONG AX * * NONE
692: ADR LONG
693: * *
694: [ZCMP] [HI AL],[CONST 0]
695: [REL1] [LAB]
696:
697: % PLE
698: LONG NONE * * NONE
699: RREG|MMX LONG
700: * *
701: [ZOR] [HI AL],[HI AL]
702: [ZJS] [LAB]
703: [ZJNE] [LAB0]
704: [ZOR] [LO AL],[LO AL]
705: [ZJE] [LAB]
706: [DLAB0]:
707:
708: % PLE
709: LONG AX * * NONE
710: ADR LONG
711: * *
712: [ZCMP] [HI AL],[CONST 0]
713: [ZJS] [LAB]
714: [ZJNE] [LAB0]
715: [ZCMP] [LO AL],[CONST 0]
716: [ZJE] [LAB]
717: [DLAB0]:
718:
719: % PGT
720: LONG NONE * * NONE
721: RREG|MMX LONG
722: * *
723: [ZOR] [HI AL],[HI AL]
724: [ZJS] [LAB0]
725: [ZJNE] [LAB]
726: [ZOR] [LO AL],[LO AL]
727: [ZJNE] [LAB]
728: [DLAB0]:
729:
730: % PGT
731: LONG AX * * NONE
732: ADR LONG
733: * *
734: [ZCMP] [HI AL],[CONST 0]
735: [ZJS] [LAB0]
736: [ZJNE] [LAB]
737: [ZCMP] [LO AL],[CONST 0]
738: [ZJNE] [LAB]
739: [DLAB0]:
740:
741: #ifdef NDPDEF
742: % PREL
743: FF64 * * * NONE
744: RREG|MMX FF64
745: * *
746: [CALL] [GID tstccp]
747: [REL0] [LAB]
748: #endif
749:
750: #ifndef ONLYSMALL
751: % PEREL
752: LPTX * * * NONE
753: RREG|MMX LPTX
754: * *
755: [ZOR] [LO AL],[HI AL]
756: [REL0] [LAB]
757:
758: % PEREL
759: LPTX AX * * NONE
760: ADR LPTX
761: * *
762: [ZMOV] [R],[HI AL]
763: [ZOR] [R],[LO AL]
764: [REL0] [LAB]
765:
766: % PREL
767: LPTX AX * * NONE
768: ADR LPTX
769: * *
770: [ZCMP] [LO AL],[CONST 0]
771: [REL0] [LAB]
772: #endif
773:
774: % PUGE
775: * NONE * * NONE
776: * *
777: * *
778: [ZJMP] [LAB]
779:
780: % PULT
781: * NONE * * NONE
782: * *
783: * *
784: ;
785:
786: % PSREL
787: WORD NONE ANYR * NONE
788: TREG WORD
789: * *
790: [ZOR] [RL],[RL]
791: [REL0] [LAB]
792:
793: #ifndef ONLYSMALL
794: % PEREL
795: LPTX NONE ANYR * NONE
796: TREG LPTX
797: * *
798: [ZOR] [LO RL],[HI RL]
799: [REL0] [LAB]
800:
801: % PREL
802: LPTX NONE ANYR * NONE
803: TREG LPTX
804: * *
805: [ZOR] [LO RL],[LO RL]
806: [REL0] [LAB]
807: #endif
808:
809: #ifndef NDPDEF
810: //////////
811: /
812: / The ddtest() call generated by the first entry below is necessary
813: / because of the nonaddressability of FPAC in LARGE model.
814: / It should be conditionalized #ifndef ONLYSMALL,
815: / but tabgen currently does not process nested conditionals correctly.
816: / It is not required for SMALL model but I cannot figure out how to avoid it.
817: /
818: //////////
819:
820: % PREL
821: FF64 NONE * * NONE
822: RREG|MMX FF64
823: * *
824: [CALL] [GID ddtest]
825: [REL0] [LAB]
826:
827: % PREL
828: FF64 NONE * * NONE
829: ADR FF64
830: * *
831: [ZTEST] [HI LO AL],[CONST 077600]
832: [REL0] [LAB]
833:
834: % PREL
835: FF32|FF64 NONE * * NONE
836: ADR FF32
837: * *
838: [ZTEST] [HI AL],[CONST 077600]
839: [REL0] [LAB]
840:
841: #endif
842:
843: /////////
844: /
845: / Push function arguments onto the stack.
846: / For the 8086, this is complicated by the lack of a push immediate.
847: / Perhaps the "make an addr" conversion should be performed.
848: / For the i80186, similar but using push immediate.
849: /
850: /////////
851: % PFNARG|P80186
852: WORD NONE * * NONE
853: IMM|MMX WORD
854: * *
855: [ZPUSH] [AL]
856:
857: % PFNARG
858: WORD ANYR * * NONE
859: 0|MMX *
860: * *
861: [ZSUB] [R],[R]
862: [ZPUSH] [R]
863:
864: % PFNARG
865: WORD ANYR * * NONE
866: IMM|MMX WORD
867: * *
868: [ZMOV] [R],[AL]
869: [ZPUSH] [R]
870:
871: % PFNARG
872: WORD ANYR * * NONE
873: LEA|MMX WORD
874: * *
875: [ZLEA] [R],[NSE AL]
876: [ZPUSH] [R]
877:
878: #ifndef ONLYSMALL
879: % PFNARG
880: LPTX ANYR * * NONE
881: LSS|MMX LPTX
882: * *
883: [ZPUSH] [REGNO SS]
884: [ZLEA] [LO R],[NSE AL]
885: [ZPUSH] [LO R]
886:
887: % PFNARG|P80186
888: LPTX NONE * * NONE
889: ICN|MMX LPTX
890: * *
891: [ZPUSH] [CONST 0]
892: [ZPUSH] [AL]
893:
894: % PFNARG|P80186
895: LPTX NONE * * NONE
896: LCN|MMX LPTX
897: * *
898: [ZPUSH] [HI AL]
899: [ZPUSH] [LO AL]
900:
901: % PFNARG
902: LPTX AX * * NONE
903: 0|MMX *
904: * *
905: [ZSUB] [R],[R]
906: [ZPUSH] [R]
907: [ZPUSH] [R]
908:
909: % PFNARG
910: LPTX AX * * NONE
911: ICN|MMX LPTX
912: * *
913: [ZSUB] [R],[R]
914: [ZPUSH] [R]
915: [ZMOV] [R],[AL]
916: [ZPUSH] [R]
917:
918: % PFNARG
919: LPTX AX * * NONE
920: LCN|MMX LPTX
921: * *
922: [ZMOV] [R],[HI AL]
923: [ZPUSH] [R]
924: [ZMOV] [R],[LO AL]
925: [ZPUSH] [R]
926:
927: % PFNARG|P80186
928: LPTX NONE * * NONE
929: ACS|MMX LPTX
930: * *
931: [ZPUSH] [REGNO CS]
932: [ZPUSH] [AL]
933:
934: % PFNARG|P80186
935: LPTX NONE * * NONE
936: ADS|MMX LPTX
937: * *
938: [ZPUSH] [REGNO DS]
939: [ZPUSH] [AL]
940:
941: % PFNARG
942: LPTX ANYR * * NONE
943: ACS|MMX LPTX
944: * *
945: [ZPUSH] [REGNO CS]
946: [ZMOV] [LO R],[AL]
947: [ZPUSH] [LO R]
948:
949: % PFNARG
950: LPTX ANYR * * NONE
951: ADS|MMX LPTX
952: * *
953: [ZPUSH] [REGNO DS]
954: [ZMOV] [LO R],[AL]
955: [ZPUSH] [LO R]
956:
957: #endif
958:
959: % PFNARG
960: WORD NONE * * NONE
961: ADR WORD
962: * *
963: % PFNARG
964: BYTE * * * NONE
965: RREG|MMX WORD|BYTE
966: * *
967: [ZPUSH] [AL]
968:
969: % PFNARG|P80186
970: LONG NONE * * NONE
971: IMM|MMX LONG
972: * *
973: [ZPUSH] [HI AL]
974: [ZPUSH] [LO AL]
975:
976: % PFNARG
977: LONG|LPTX ANYR * * NONE
978: 0|MMX *
979: * *
980: [ZSUB] [LO R],[LO R]
981: [ZPUSH] [LO R]
982: [ZPUSH] [LO R]
983:
984: % PFNARG
985: LONG ANYR * * NONE
986: IMM|MMX LONG
987: * *
988: [ZMOV] [LO R],[HI AL]
989: [ZPUSH] [LO R]
990: [ZMOV] [LO R],[LO AL]
991: [ZPUSH] [LO R]
992:
993: % PFNARG
994: LONG|LPTX NONE * * NONE
995: ADR LONG|LPTX
996: * *
997: #ifndef ONLYSMALL
998: % PFNARG
999: LPTX NONE * * NONE
1000: RREG|MMX LPTX
1001: * *
1002: #endif
1003: [ZPUSH] [HI AL]
1004: [ZPUSH] [LO AL]
1005:
1006: /////////
1007: /
1008: / Floating point.
1009: /
1010: /////////
1011:
1012: #ifdef NDPDEF
1013: % PFNARG
1014: FF64 NONE * * NONE
1015: RREG|MMX FF64
1016: * *
1017: [CALL] [GID dp87]
1018: #endif
1019: #ifndef NDPDEF
1020: % PFNARG
1021: FF64 NONE * * NONE
1022: RREG|MMX FF64
1023: * *
1024: [CALL] [GID dpush]
1025:
1026: % PFNARG
1027: FF64 NONE * * NONE
1028: ADR FF64
1029: * *
1030: [ZPUSH] [HI LO AL]
1031: [ZPUSH] [LO LO AL]
1032: [ZPUSH] [HI HI AL]
1033: [ZPUSH] [LO HI AL]
1034: #endif
1035:
1036: ////////
1037: /
1038: / This entry ignores structs used for effect.
1039: /
1040: ////////
1041:
1042: % PEFFECT
1043: FBLK NONE * * NONE
1044: ADR|IMM FBLK
1045: * *
1046: ;
1047:
1048: ////////
1049: /
1050: / These tables transform value contexts into effect contexts.
1051: / They are used to clear the stack of the 8087.
1052: / The EMPTY tables are needed because the CALL node always produces a value.
1053: /
1054: ////////
1055:
1056: % PEFFECT
1057: NFLT NONE * * NONE
1058: RREG|MMX NFLT
1059: * *
1060: ;
1061:
1062: #ifndef NDPDEF
1063: % PEFFECT
1064: FF64 NONE * * NONE
1065: RREG|MMX FF64
1066: * *
1067: ;
1068: #endif
1069: #ifdef NDPDEF
1070: % PEFFECT
1071: FF64 NONE * * NONE
1072: RREG|MMX FF64
1073: * *
1074: [ZFDROP]
1075: #endif
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