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1.1 ! root 1: ///////// ! 2: / ! 3: / Shift right. This is longer than the code table for shift left because ! 4: / signed and unsigned shift right generate different code. ! 5: / The table must be different from the left shift code table ! 6: / in any case (even if a conditional were added for signed and unsigned) ! 7: / because the halves of long integers get swapped around. ! 8: / Short shifts (by 1 or 2 for 8086, by byte for 80286) are done inline. ! 9: / Longer shifts load CL with the shift count and use a variable bit shift. ! 10: / Longs are more difficult; a short loop is compiled to do the shift. ! 11: / ! 12: ///////// ! 13: ! 14: SHR: ! 15: % PEFFECT|PRVALUE|PREL|P_SLT|P80186 ! 16: WORD ANYR ANYR * TEMP ! 17: TREG FS16 ! 18: BYTE|MMX WORD ! 19: [ZSAR] [R],[AR] ! 20: [IFR] [REL0] [LAB] ! 21: ! 22: % PEFFECT|PRVALUE|PREL|P_SLT|P80186 ! 23: WORD ANYR ANYR * TEMP ! 24: TREG UWORD ! 25: BYTE|MMX WORD ! 26: [ZSHR] [R],[AR] ! 27: [IFR] [REL0] [LAB] ! 28: ! 29: % PEFFECT|PRVALUE|PREL|P_SLT ! 30: WORD ANYR ANYR * TEMP ! 31: TREG FS16 ! 32: 1|MMX * ! 33: [ZSAR] [R],[CONST 1] ! 34: [IFR] [REL0] [LAB] ! 35: ! 36: % PEFFECT|PRVALUE|PREL|P_SLT ! 37: WORD ANYR ANYR * TEMP ! 38: TREG FS16 ! 39: 2|MMX * ! 40: [ZSAR] [R],[CONST 1] ! 41: [ZSAR] [R],[CONST 1] ! 42: [IFR] [REL0] [LAB] ! 43: ! 44: % PEFFECT|PRVALUE|PREL|P_SLT ! 45: WORD ANYR ANYR * TEMP ! 46: TREG UWORD ! 47: 1|MMX * ! 48: [ZSHR] [R],[CONST 1] ! 49: [IFR] [REL0] [LAB] ! 50: ! 51: % PEFFECT|PRVALUE|PREL|P_SLT ! 52: WORD ANYR ANYR * TEMP ! 53: TREG UWORD ! 54: 2|MMX * ! 55: [ZSHR] [R],[CONST 1] ! 56: [ZSHR] [R],[CONST 1] ! 57: [IFR] [REL0] [LAB] ! 58: ! 59: ///////// ! 60: / ! 61: / Non trivial word shifts. ! 62: / Load CL with count and use variable format shift instruction. ! 63: / If right is a constant, use a MOVB to load CL; saves a byte. ! 64: / ! 65: ///////// ! 66: % PEFFECT|PRVALUE|PREL|P_SLT ! 67: WORD AX AX CX TEMP ! 68: TREG FS16 ! 69: IMM|MMX WORD ! 70: [ZMOVB] [REGNO CL],[AR] ! 71: [ZSAR] [R],[REGNO CL] ! 72: [IFR] [REL0] [LAB] ! 73: ! 74: % PEFFECT|PRVALUE|PREL|P_SLT ! 75: WORD AX AX CX TEMP ! 76: TREG UWORD ! 77: IMM|MMX WORD ! 78: [ZMOVB] [REGNO CL],[AR] ! 79: [ZSHR] [R],[REGNO CL] ! 80: [IFR] [REL0] [LAB] ! 81: ! 82: % PEFFECT|PRVALUE|P_SLT ! 83: WORD ANYR ANYR CX TEMP ! 84: TREG FS16 ! 85: ADR WORD ! 86: [ZMOV] [REGNO CX],[AR] ! 87: [ZSAR] [R],[REGNO CL] ! 88: ! 89: % PEFFECT|PRVALUE|P_SLT ! 90: WORD ANYR ANYR CX TEMP ! 91: TREG UWORD ! 92: ADR WORD ! 93: [ZMOV] [REGNO CX],[AR] ! 94: [ZSHR] [R],[REGNO CL] ! 95: ! 96: ///////// ! 97: / ! 98: / Non trivial long shifts. ! 99: / Load count to CX and use a loop. ! 100: / Shifts of 0 have been deleted by the optimizer; ! 101: / this means the JCXZ instruction is not needed if the right ! 102: / operand is a constant. ! 103: / ! 104: ///////// ! 105: ! 106: % PEFFECT|PRVALUE|P_SLT ! 107: LONG DXAX DXAX CX DXAX ! 108: TREG FS32 ! 109: IMM|MMX WORD ! 110: [ZMOV] [REGNO CX],[AR] ! 111: [DLAB0]:[ZSAR] [HI R],[CONST 1] ! 112: [ZRCR] [LO R],[CONST 1] ! 113: [ZLOOP] [LAB0] ! 114: ! 115: % PEFFECT|PRVALUE|P_SLT ! 116: LONG DXAX DXAX CX DXAX ! 117: TREG FU32 ! 118: IMM|MMX WORD ! 119: [ZMOV] [REGNO CX],[AR] ! 120: [DLAB0]:[ZSHR] [HI R],[CONST 1] ! 121: [ZRCR] [LO R],[CONST 1] ! 122: [ZLOOP] [LAB0] ! 123: ! 124: % PEFFECT|PRVALUE|P_SLT ! 125: LONG ANYR ANYR CX TEMP ! 126: TREG FS32 ! 127: ADR WORD ! 128: [ZMOV] [REGNO CX],[AR] ! 129: [ZJCXZ] [LAB0] ! 130: [DLAB1]:[ZSAR] [HI R],[CONST 1] ! 131: [ZRCR] [LO R],[CONST 1] ! 132: [ZLOOP] [LAB1] ! 133: [DLAB0]: ! 134: ! 135: % PEFFECT|PRVALUE|P_SLT ! 136: LONG ANYR ANYR CX TEMP ! 137: TREG FU32 ! 138: ADR WORD ! 139: [ZMOV] [REGNO CX],[AR] ! 140: [ZJCXZ] [LAB0] ! 141: [DLAB1]:[ZSHR] [HI R],[CONST 1] ! 142: [ZRCR] [LO R],[CONST 1] ! 143: [ZLOOP] [LAB1] ! 144: [DLAB0]:
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