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1.1 root 1: /* (-lgl
2: * COHERENT 386 Device Driver Kit release 2.0
3: * Copyright (c) 1982, 1992 by Mark Williams Company.
4: * All rights reserved. May not be copied without permission.
5: -lgl) */
6: #ifndef __SYS_AHA154X_H__
7: #define __SYS_AHA154X_H__
8:
9: /*
10: * describe the data structures neccessary to
11: * access the Hard/Firmware of the AHA-154x family.
12: *
13: * First the hardware which consists of three I/O ports.
14: */
15:
16: #define AHA_CONTROL (0*0+0)
17: #define AHA_HARDRESET 0x80 /* Hard */
18: #define AHA_SOFTRESET 0x40 /* Soft */
19: #define AHA_INTRRESET 0x20 /* Interrupt */
20: #define AHA_SCSIRESET 0x10 /* SCSI */
21: /* ... Reserved ... */
22:
23: #define AHA_STATUS (0*0+0)
24: #define AHA_SELFTEST 0x80 /* SELF TEST in progress */
25: #define AHA_DIAGFAIL 0x40 /* DIAGnostics FAILed */
26: #define AHA_INITMAIL 0x20 /* INIT of MAILbox required */
27: #define AHA_SCSIIDLE 0x10 /* SCSI host adaptor IDLE */
28: #define AHA_CDOPFULL 0x08 /* Command/Data Out Port FULL */
29: #define AHA_DIPFULL 0x04 /* Data In Port FULL */
30: /* ... Reserved ... */
31: #define AHA_INVDCMD 0x01 /* INValiD CoMmanD */
32:
33: #define AHA_READ (0*0+1)
34: #define AHA_WRITE (0*0+1)
35:
36: #define AHA_INTERRUPT (0*0+2)
37: #define AHA_ANY_INTER 0x80
38: /* ... Reserved ... */
39: #define AHA_RESETED 0x08
40: #define AHA_CMD_DONE 0x04
41: #define AHA_MBO_EMPTY 0x02
42: #define AHA_MBI_STORED 0x01
43: #define AHA_ALL_INTERRUPTS \
44: (AHA_RESETED|AHA_CMD_DONE|AHA_MBO_EMPTY|AHA_MBI_STORED)
45:
46: /*
47: * Command Control Block Opcodes.
48: */
49: #define AHA_OP_SIC 0x00 /* SCSI Initiator Command Control Block */
50: #define AHA_OP_TCC 0x01 /* SCSI Target Command Control Block */
51: #define AHA_OP_SIC_SG 0x02 /* SCSI Initiator Command Control Block
52: * with Scatter/Gather */
53: #define AHA_OP_SIC_res 0x03 /* SCSI Initiator Command,
54: * residual data length returned. */
55: #define AHA_OP_SIC_SG_res 0x04 /* SCSI Initiator Command
56: * with Scatter/Gather,
57: * residual data length returned. */
58: #define AHA_OP_SPQR 0x81 /* SCSI Bus Device Reset
59: * (a work of the people :-) */
60: #define AHA_OP_INVALID 0x22 /* This randomly chosen command is used to
61: * mark a ccb as invalidated. */
62:
63: /*
64: * Adapter Firmware Components
65: */
66: #define AHA_DO_NOP 0x00
67: #define AHA_DO_MAILBOX_INIT 0x01
68: /* DATA send = MB count, MB adr[3] */
69: #define AHA_DO_SCSI_START 0x02
70: #define AHA_DO_BIOS_START 0x03
71: #define AHA_DO_INQUIRY 0x04
72: /* DATA recv = board id (ASCII)
73: special options id (standard = 'A')
74: HW rev level (ASCII)
75: FirmWare rev level (ASCII)*/
76: #define AHA_DO_MBO_INTR_ON 0x05
77: /* DATA send = 0/1 = Dis/Enable INTR */
78: #define AHA_DO_SET_TIMEOUT 0x06
79: /* DATA send = 0/1 = Dis/Enable Timeout
80: ...reserved...
81: value[MSB] default = 250 millisec
82: value[LSB] */
83: #define AHA_DO_BUS_ON_TIME 0x07
84: /* DATA send = 2 to 15 microsec. */
85: #define AHA_DO_BUS_OFF_TIME 0x08
86: /* DATA send = 1 to 64 microsec. */
87: #define AHA_DO_XFER_SPEED 0x09
88: #define AHA_SPEED_5_0_MB 0x00
89: #define AHA_SPEED_6_7_MB 0x01
90: #define AHA_SPEED_8_0_MB 0x02
91: #define AHA_SPEED_10_MB 0x03
92: #define AHA_SPEED_5_7_MB 0x04
93: #define AHA_SPEED_CUSTOM 0x80
94: /* see Chap. 5.1.1.10 */
95: #define AHA_DO_GET_DEVICES 0x0A
96: /* DATA recv = eight bytes, one per target
97: whereby each bit indicates if a LUN is installed */
98: #define AHA_DO_GET_CONFIG 0x0B
99: /* DATA recv = DMA Arb. Priority,
100: Inter. Channel,
101: SCSI Id. */
102: #define AHA_DO_TARGET_ON 0x0C
103: /* DATA send = 0/1 = Dis/Enable Target Mode
104: LUN mask, 1 -> LUN will respond in Target Mode */
105: #define AHA_DO_GET_SETUP 0x0D
106: /* DATA send = n, count requested, 0 -> 256 bytes
107: DATA recv = 00 SDT + Parity,
108: 01 Transfer Speed,
109: 02 Bus On Time,
110: 03 Bus Off Time,
111: 04 # MB's,
112: 05-07 MailBox Adr,
113: 08-0F Sync Transfer Agreements,
114: 10-FF Reserved (default 00) */
115:
116: /* ... reserved ... */
117: #define AHA_DO_PUT_CH2_BUF 0x1A
118: /* DATA send = 00-02 Buffer Area (64 bytes) Address */
119: #define AHA_DO_GET_CH2_BUF 0x1B
120: /* DATA send = 00-02 Buffer Area (64 bytes) Address */
121: #define AHA_DO_PUT_FIFO_BUF 0x1C
122: /* DATA send = 00-02 FIFO Area (54 bytes) Address */
123: #define AHA_DO_GET_FIFO_BUF 0x1D
124: /* DATA send = 00-02 FIFO Area (54 bytes) Address */
125: /* ... reserved ... */
126: #define AHA_DO_ECHO_CMD_DATA 0x1F
127: /* DATA send = 1 byte
128: DATA recv = 1 byte, hopefully the same one ! */
129:
130: /* A P3 is a 3 byte physical address. */
131: typedef unsigned char P3[3];
132:
133: typedef struct {
134: # define MBO_IS_FREE 0x00
135: # define MBO_TO_START 0x01
136: # define MBO_IS_ABORT 0x02
137: char state;
138: P3 ccb_adr;
139: } MBO;
140:
141: /*
142: * MBI for CCB completed
143: */
144: typedef struct {
145: # define MBI_IS_FREE 0x00
146: # define MBI_NO_ERROR 0x01
147: # define MBI_IS_ABORT 0x02
148: # define MBI_NOT_FOUND 0x03
149: # define MBI_HAS_ERROR 0x04
150: char state;
151: /* MBI for CCB required */
152: /* byte 0 */
153: # define MBI_CCB_REQUEST 0x10
154: /* byte 1 */
155: # define MBI_MSK_INITOR 0xE0
156: # define MBI_WAS_READ 0x10
157: # define MBI_WAS_WRITE 0x08
158: # define MBI_MSK_LUN 0x03
159: /* byte 2,3 are data len */
160: P3 ccb_adr;
161: } MBI;
162:
163: #ifndef MAX_SCSICMD
164: #define MAX_SCSICMD 14
165: #endif /* MAX_SCSICMD */
166:
167: #ifndef MAX_SENSEDATA
168: #define MAX_SENSEDATA 27
169: #endif /* MAX_SENSEDATA */
170:
171: typedef struct {
172: unsigned char cmd;
173: P3 adr;
174: } mailentry;
175:
176: #define SENSE_UNIT_ATTENTION 6
177: #define CHECK_TARGET_STATUS 2
178: typedef struct {
179: char opcode;
180: char target;
181: #define AHA_CCB_DATA_OUT 0x10
182: #define AHA_CCB_DATA_IN 0x08
183: char cmdlen;
184: char senselen;
185: P3 datalen;
186: P3 dataptr;
187: P3 linkptr;
188: char linkid;
189: char hoststatus;
190: char targetstatus;
191: char reserve[2];
192: unsigned char cmd_status[MAX_SCSICMD+MAX_SENSEDATA];
193: scsi_work_t *ccb_sw;
194: unsigned char buffer[1];
195: } ccb_t;
196:
197: #ifdef _I386
198: /* These macros are for stashing away P3 addresses for ccbs. */
199: #define ccb_forget( a_ccb ) mem_forget( a_ccb )
200: #define ccb_remember( a_ccb, a_p3 ) \
201: mem_remember( (a_ccb), aha_p3_to_l( a_p3 ) )
202: #define ccb_recall( a_p3 ) mem_recall( aha_p3_to_l( a_p3 ) )
203:
204: typedef struct {
205: P3 size;
206: P3 addr;
207: } DSL_ENTRY;
208: #endif /* _I386 */
209:
210: #endif /* of AHA154X_H */
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