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1.1 root 1: /* (-lgl
2: * COHERENT 386 Device Driver Kit release 2.0
3: * Copyright (c) 1982, 1992 by Mark Williams Company.
4: * All rights reserved. May not be copied without permission.
5: -lgl) */
6: /*
7: * INS 8250 ACIA Register Definitions
8: */
9: #ifndef __SYS_INS8250_H__
10: #define __SYS_INS8250_H__
11:
12: /*
13: * Register Offsets
14: */
15:
16: #define DREG 0 /* Data Register (DLAB=0) */
17: #define IER 1 /* Interrupt Enable Register (DLAB=0) */
18: #define IIR 2 /* Interrupt Identification Register */
19: #define FCR 2 /* FIFO Control Register */
20: #define LCR 3 /* Line Control Register */
21: #define MCR 4 /* Modem Control Register */
22: #define LSR 5 /* Line Status Register */
23: #define MSR 6 /* Modem Status Register */
24: #define SCR 7 /* Scratch Register */
25:
26: #define DLL 0 /* Divisor Latch Low Register (DLAB=1) */
27: #define DLH 1 /* Divisor Latch High Register (DLAB=1) */
28:
29: /*
30: * Interrupt Enable Register (IER) - bits 4-7 zeroed
31: */
32:
33: #define IE_RxI 0x01 /* Enable Received Data Available Intr. */
34: #define IE_TxI 0x02 /* Enable Transmit Buf Empty Interrupt */
35: #define IE_LSI 0x04 /* Enable Line Status Interrupt */
36: #define IE_MSI 0x08 /* Enable Modem Status Interrupt */
37:
38: #define IENABLE (IE_RxI | IE_TxI | IE_LSI | IE_MSI)
39:
40:
41: /*
42: * Interrupt Identification Register (IIR)
43: */
44:
45: #define Rt_INTR 0x0C /* Received Char Timeout Interrupt */
46: #define LS_INTR 0x06 /* Receiver Line Status Interrupt */
47: #define Rx_INTR 0x04 /* Received Data Available Interrupt */
48: #define Tx_INTR 0x02 /* Transmit Buf Empty Interrupt */
49: #define MS_INTR 0x00 /* Modem Status Interrupt */
50:
51:
52: /*
53: * FIFO Control Register (FCR)
54: */
55:
56: #define FC_ENABLE 0x01 /* Enable on-chip FIFO (16550A only) */
57: #define FC_Rx_RST 0x02 /* Reset RCVR FIFO */
58: #define FC_Tx_RST 0x04 /* Reset XMIT FIFO */
59: #define FC_Rx_01 0x00 /* Rx Irpt on 1 char in rcvr FIFO */
60: #define FC_Rx_04 0x40 /* Rx Irpt on 4 char in rcvr FIFO */
61: #define FC_Rx_08 0x80 /* Rx Irpt on 8 char in rcvr FIFO */
62: #define FC_Rx_14 0xC0 /* Rx Irpt on 14 char in rcvr FIFO */
63:
64: /*
65: * Line Control Register (LCR)
66: */
67:
68: #define LC_CSIZE 0x03 /* Character Size: */
69: #define LC_CS5 0 /* 5 bits */
70: #define LC_CS6 0x01 /* 6 bits */
71: #define LC_CS7 0x02 /* 7 bits */
72: #define LC_CS8 0x03 /* 8 bits */
73:
74: #define LC_STOPB 0x04 /* 1 1/2 (CS5) or 2 (CS6-CS8) stop bits */
75: #define LC_PARENB 0x08 /* Parity Enable */
76:
77: #define LC_PARITY 0x30 /* Parity Selection: */
78: #define LC_PARODD 0 /* Odd Parity */
79: #define LC_PAREVEN 0x10 /* Even Parity */
80: #define LC_PARLO 0x20 /* Low Stick */
81: #define LC_PARHI 0x30 /* High Stick */
82: #define LC_SBRK 0x40 /* Set Break */
83: #define LC_DLAB 0x80 /* Divisor Latch Access Bit (DLAB) */
84:
85: /*
86: * Modem Control Register (MCR) - bits 5..7 zeroed
87: */
88: #define MC_DTR 0x01 /* Data Terminal Ready */
89: #define MC_RTS 0x02 /* Request to Send */
90: #define MC_OUT1 0x04 /* Auxiliary user-designated output 1 */
91: #define MC_OUT2 0x08 /* Auxiliary user-designated output 2 */
92: #define MC_OUTS 0x0C /* Both OUT signals */
93: #define MC_LOOP 0x10 /* Loopback enable (diagnostic feature) */
94:
95: /*
96: * Line Status Register (LSR) - bit 7 zeroed
97: */
98: #define LS_RxRDY 0x01 /* Receiver Data Ready */
99: #define LS_OVER 0x02 /* Overrun Error */
100: #define LS_PARITY 0x04 /* Parity Error */
101: #define LS_FRAME 0x08 /* Framing Error */
102: #define LS_BREAK 0x10 /* Break Interrupt Indicator */
103: #define LS_TxRDY 0x20 /* Transmitter Ready for Data */
104: #define LS_TxIDLE 0x40 /* Transmitter Idle */
105:
106: /*
107: * Modem Status Register (MSR)
108: */
109: #define MS_DCTS 0x01 /* Delta Clear to Send */
110: #define MS_DDSR 0x02 /* Delta Data Set Ready */
111: #define MS_TERI 0x04 /* Trailing Edge of Ring Indicator */
112: #define MS_DRLSD 0x08 /* Delta Rx Line Signal Detect */
113: #define MS_CTS 0x10 /* Clear To Send */
114: #define MS_DSR 0x20 /* Data Set Ready */
115: #define MS_RI 0x40 /* Ring Indicator */
116: #define MS_RLSD 0x80 /* Receive Line Signal Detect */
117:
118: /*
119: * Uart-sense types.
120: */
121: #define US_NONE 0
122: #define US_8250 1
123: #define US_16450 2
124: #define US_16550 3
125: #define US_16550A 4 /* The only one with usable on-chip FIFO */
126: #define US_UNKNOWN -1
127:
128: #endif
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