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Annotation of coherent/f/usr/include.78/sys/m18hd.h, revision 1.1.1.1

1.1       root        1: /* $Header: /usr/src/sys/i8086/sys/RCS/m18hd.h,v 1.1 88/03/24 17:48:25 src Exp $
                      2:  *
                      3:  * Olivetti M18 Personal Computer
                      4:  * Hard Disk Constants
                      5:  *
                      6:  *                     Allan Cornish, INETCO Systems Ltd., Aug 1984
                      7:  *
                      8:  * $Log:       /usr/src/sys/i8086/sys/RCS/m18hd.h,v $
                      9:  * Revision 1.1        88/03/24  17:48:25      src
                     10:  * Initial revision
                     11:  * 
                     12:  */
                     13: #ifndef M18HD_H
                     14: #define        M18HD_H
                     15: 
                     16: /*
                     17:  * Register Addresses
                     18:  */
                     19: 
                     20: #define        SEL_REG         0x300           /* Select Register (write only) */
                     21: #define        STAT_REG        0x300           /* Status Register (read  only) */
                     22: #define        ENA_REG         0x301           /* Enable Register (write only) */
                     23: #define        DATA_REG        0x302           /* Data   Register (read/write) */
                     24: #define        CMD_REG         0x303           /* Commnd Register (read,write) */
                     25: #define        AUX_REG         0x304           /* Auxiliary Reg   (read  only) */
                     26:  
                     27: /*
                     28:  * Select Register (Write Only)
                     29:  */
                     30: 
                     31: #define        HEAD_SEL(n)     ((n)<<2)        /* Head Select macro            */
                     32: #define        STEP_SEL        0x20            /* Set to step                  */
                     33: #define        STEP_IN         0x40            /* Set to step in               */
                     34: #define        RWC_SEL         0x80            /* Reduced Write Curr           */
                     35:  
                     36: /*
                     37:  * Status Register (Read Only) - bits 6..7 unused
                     38:  */
                     39: 
                     40: #define        DTA_ST          0x01            /* Drive Type, Jumper A         */
                     41: #define        RDY_ST          0x02            /* Drive Ready                  */
                     42: #define        TK0_ST          0x04            /* At Track 0                   */
                     43: #define        WFLT_ST         0x08            /* Write Fault on drive         */
                     44: #define        SKC_ST          0x10            /* Seek Complete                */
                     45: #define        SYNC_ST         0x20            /* Sector Synchronization       */
                     46: 
                     47: /*
                     48:  * Enable Register (Write Only) - bits 0..4 select sector (0..31)
                     49:  */
                     50: 
                     51: #define        READ_ENA        0x20            /* Enable read as next command  */
                     52: #define        ECC_ENA         0x40            /* Enable ecc on next command   */
                     53: #define        WPRE_ENA        0x80            /* Enable write precompensation */
                     54: 
                     55: /*
                     56:  * Auxiliary Register (Read Only) - bits 2..7 unused
                     57:  */
                     58: 
                     59: #define        BUSY_AUX        0x01            /* Drive Busy                   */
                     60: #define        DTC_AUX         0x02            /* Drive Type, Jumper C         */
                     61: 
                     62: /*
                     63:  * Drive Specific Constants
                     64:  */
                     65: 
                     66: #define        NSPT            32
                     67: #define        NHEAD           4
                     68: #define        NCYL            306
                     69: #define        WPCC            64              /* Write Precompensation cyl    */
                     70: #define        RWCC            128             /* Reduced Write Current cyl    */
                     71: 
                     72: /*
                     73:  * Error Returns from hdget(), hdput()
                     74:  */
                     75: 
                     76: #define        ECC_ERR         0x00ff          /* Bad ECC read error mask      */
                     77: #define        SKNC_ERR        0x0100          /* Seek Not Complete Error      */
                     78: #define        BUSY_ERR        0x0200          /* Controller Busy Error        */
                     79: #define        SYNC_ERR        0x0400          /* Synchronization Error        */
                     80: #define        PRFX_ERR        0x0800          /* Bad Prefix Read Error        */
                     81: #define        HEAD_ERR        0x1000          /* Bad Head Read Error          */
                     82: #define        CYL_ERR         0x2000          /* Bad Cylinder Read Error      */
                     83: #define        SEC_ERR         0x4000          /* Bad Sector ID Read Error     */
                     84: #define        NRDY_ERR        0x8000          /* Drive Not Ready Error        */
                     85: 
                     86: 
                     87: #endif

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