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Annotation of coherent/f/usr/include.78/sys/xl8237.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * /usr/include/sys/xl8237.h
        !             3:  *
        !             4:  * DMA compatibility for Archive floppy tape.
        !             5:  * This header will disappear soon!
        !             6:  *
        !             7:  * Revised: Mon May 24 17:30:27 1993 CDT
        !             8:  */
        !             9: #ifndef _SYS_I8237A_H
        !            10: #define        _SYS_I8237A_H
        !            11: 
        !            12: #define D37A_MAX_CHAN   8
        !            13: #define D37A_DFR_ALIGN  0xf
        !            14: #define D37A_MIN_CHAN   0x0
        !            15: 
        !            16: /*
        !            17:  * Defines for PC AT DMA controllers.
        !            18:  * The PC AT has two intel 8237A-5 dma controllers with page registers
        !            19:  * for each channel, allowing access to the entire 16M address space.
        !            20:  */
        !            21: 
        !            22: #define DMACH0PG        0x87    /* port address for dma chan. 0 page reg. */
        !            23: #define DMACH1PG        0x83    /* port address for dma chan. 1 page reg. */
        !            24: #define DMACH2PG        0x81    /* port address for dma chan. 2 page reg. */
        !            25: #define DMACH3PG        0x82    /* port address for dma chan. 3 page reg. */
        !            26: #define DMACH4PG        0x00    /* dummy address for dma chan. 4 page reg. */
        !            27: #define DMACH5PG        0x8b    /* port address for dma chan. 5 page reg. */
        !            28: #define DMACH6PG        0x89    /* port address for dma chan. 6 page reg. */
        !            29: #define DMACH7PG        0x8a    /* port address for dma chan. 7 page reg. */
        !            30: 
        !            31: /*
        !            32:  * The EISA has a high page address register giving access to the
        !            33:  *      full 32-bit address space
        !            34:  */
        !            35: 
        !            36: #define DMACH0HPG       0x487   /* port address for dma chan. 0 high page reg */
        !            37: #define DMACH1HPG       0x483   /* port address for dma chan. 1 high page reg */
        !            38: #define DMACH2HPG       0x481   /* port address for dma chan. 2 high page reg */
        !            39: #define DMACH3HPG       0x482   /* port address for dma chan. 3 high page reg */
        !            40: #define DMACH4HPG       0x000   /* dumy address for dma chan. 4 high page reg */
        !            41: #define DMACH5HPG       0x48b   /* port address for dma chan. 5 high page reg */
        !            42: #define DMACH6HPG       0x489   /* port address for dma chan. 6 high page reg */
        !            43: #define DMACH7HPG       0x48a   /* port address for dma chan. 7 high page reg */
        !            44: 
        !            45: /*
        !            46:  * I/O port addresses for controller 1 programming.
        !            47:  */
        !            48: #define DMA1BCA0        0x00    /* chan. 0 base and current address */
        !            49: #define DMA1BCWC0       0x01    /* chan. 0 base and current word count */
        !            50: #define DMA1BCA1        0x02    /* chan. 1 base and current address */
        !            51: #define DMA1BCWC1       0x03    /* chan. 1 base and current word count */
        !            52: #define DMA1BCA2        0x04    /* chan. 2 base and current address */
        !            53: #define DMA1BCWC2       0x05    /* chan. 2 base and current word count */
        !            54: #define DMA1BCA3        0x06    /* chan. 3 base and current address */
        !            55: #define DMA1BCWC3       0x07    /* chan. 3 base and current word count */
        !            56: #define DMA1RSWWCR      0x08    /* read status reg/write command reg */
        !            57: #define DMA1WRR         0x09    /* write request register */
        !            58: #define DMA1WSMR        0x0a    /* write single mask register bit */
        !            59: #define DMA1WMR         0x0b    /* write mode register */
        !            60: #define DMA1CBPFF       0x0c    /* clear byte pointer flip flop */
        !            61: #define DMA1RTRWMC      0x0d    /* read temp reg/write master clear */
        !            62: #define DMA1CMR         0x0e    /* clear mask register */
        !            63: #define DMA1WAMRB       0x0f    /* write all mask register bits */
        !            64: 
        !            65: /*
        !            66:  * I/O port addresses for controller 2 programming.
        !            67:  */
        !            68: #define DMA2BCA0        0xc0    /* chan. 0 base and current address */
        !            69: #define DMA2BCWC0       0xc2    /* chan. 0 base and current word count */
        !            70: #define DMA2BCA1        0xc4    /* chan. 1 base and current address */
        !            71: #define DMA2BCWC1       0xc6    /* chan. 1 base and current word count */
        !            72: #define DMA2BCA2        0xc8    /* chan. 2 base and current address */
        !            73: #define DMA2BCWC2       0xca    /* chan. 2 base and current word count */
        !            74: #define DMA2BCA3        0xcc    /* chan. 3 base and current address */
        !            75: #define DMA2BCWC3       0xce    /* chan. 3 base and current word count */
        !            76: #define DMA2RSWWCR      0xd0    /* read status reg/write command reg */
        !            77: #define DMA2WRR         0xd2    /* write request register */
        !            78: #define DMA2WSMR        0xd4    /* write single mask register bit */
        !            79: #define DMA2WMR         0xd6    /* write mode register */
        !            80: #define DMA2CBPFF       0xd8    /* clear byte pointer flip flop */
        !            81: #define DMA2RTRWMC      0xda    /* read temp reg/write master clear */
        !            82: #define DMA2CMR         0xdc    /* clear mask register */
        !            83: #define DMA2WAMRB       0xde    /* write all mask register bits */
        !            84: 
        !            85: /*
        !            86:  * defines for XENIX compatibility
        !            87:  */
        !            88: 
        !            89: /*
        !            90:  * Intel 8237 DMA Controller.
        !            91:  */
        !            92: 
        !            93: /*
        !            94:  * DMA I/O Port Assignments.
        !            95:  */
        !            96: /* 8 bit channel specific registers on controller 1 */
        !            97: #define DMA_0ADR        0x00    /* Channel  address register */
        !            98: #define DMA_0WCNT       0x01    /* Channel  word count */
        !            99: #define DMA_1ADR        0x02    /* Channel  address register */
        !           100: #define DMA_1WCNT       0x03    /* Channel  word count */
        !           101: #define DMA_2ADR        0x04    /* Channel  address register */
        !           102: #define DMA_2WCNT       0x05    /* Channel  word count */
        !           103: #define DMA_3ADR        0x06    /* Channel  address register */
        !           104: #define DMA_3WCNT       0x07    /* Channel  word count */
        !           105: 
        !           106: #define DMACH0CCH       0x401   /* chan. 0 base and current count high */
        !           107: #define DMACH1CCH       0x403   /* chan. 1 base and current count high */
        !           108: #define DMACH2CCH       0x405   /* chan. 2 base and current count high */
        !           109: #define DMACH3CCH       0x407   /* chan. 3 base and current count high */
        !           110: 
        !           111: 
        !           112: /* 16 bit channel specific registers on controller 1.
        !           113:  * Chip A0 connected to bus A1, etc. so even address 
        !           114:  * increments generated by this controller.  Hence, 
        !           115:  * 16 bit dma, and only even i/o addresses. Channel 4
        !           116:  * used to cascade controllers.
        !           117:  */
        !           118: #define DMA_4ADR        0xC0    /* (RESERVED) Channel  address register */
        !           119: #define DMA_4WCNT       0xC2    /* (RESERVED) Channel  word count */
        !           120: #define DMA_5ADR        0xC4    /* Channel  address register */
        !           121: #define DMA_5WCNT       0xC6    /* Channel  word count */
        !           122: #define DMA_6ADR        0xC8    /* Channel  address register */
        !           123: #define DMA_6WCNT       0xCA    /* Channel  word count */
        !           124: #define DMA_7ADR        0xCC    /* Channel  address register */
        !           125: #define DMA_7WCNT       0xCE    /* Channel  word count */
        !           126: 
        !           127: #define DMACH4CCH       0x000   /* dummy chan. 0 base and current count high */
        !           128: #define DMACH5CCH       0x4c6   /* chan. 1 base and current count high */
        !           129: #define DMACH6CCH       0x4ca   /* chan. 2 base and current count high */
        !           130: #define DMACH7CCH       0x4ce   /* chan. 3 base and current count high */
        !           131: 
        !           132: /* DMA controller 1, 8 bit channels */
        !           133: #define CTL1_CMD        0x08    /* Command reg */
        !           134: #define CTL1_REQ        0x09    /* request reg */
        !           135: #define CTL1_STAT       0x08    /* Status reg */
        !           136: #define CTL1_MASK       0x0A    /* Mask set/reset register */
        !           137: #define CTL1_MODE       0x0B    /* Mode reg */
        !           138: #define CTL1_CLFF       0x0C    /* Clear byte pointer first/last flip-flop */
        !           139: #define CTL1_ALLMASK    0x0F    /* Mask all registers */
        !           140: 
        !           141: #define EISA_DMAIS      0x40a   /* interrupt status regiser */
        !           142: #define CTL1_SCM        0x40a   /* set chain mode */
        !           143: #define CTL1_EWM        0x40b   /* extended write mode */
        !           144: 
        !           145: /* DMA controller 2, 16 bit channels */
        !           146: #define CTL2_CMD        0xD0    /* Command reg */
        !           147: #define CTL2_REQ        0xD2    /* request reg */
        !           148: #define CTL2_STAT       0xD0    /* Status reg */
        !           149: #define CTL2_MASK       0xD4    /* Mask set/reset register */
        !           150: #define CTL2_MODE       0xD6    /* Mode reg */
        !           151: #define CTL2_CLFF       0xD8    /* Clear byte pointer first/last flip-flop */
        !           152: #define CTL2_ALLMASK    0xDE    /* Mask all registers */
        !           153: 
        !           154: #define CTL2_SCM        0x40a   /* set chain mode */
        !           155: #define CTL2_EWM        0x40b   /* extended write mode */
        !           156: 
        !           157: /* 8 bit channels */
        !           158: #define DMA_0XADR       0x87    /* Channel 0 address extension reg */
        !           159: #define DMA_1XADR       0x83    /* Channel 1 address extension reg */
        !           160: #define DMA_2XADR       0x81    /* Channel 2 address extension reg */
        !           161: #define DMA_3XADR       0x82    /* Channel 3 address extension reg */
        !           162: 
        !           163: /* 16 bit channels */
        !           164: #define DMA_5XADR       0x8B    /* Channel 5 address extension reg */
        !           165: #define DMA_6XADR       0x89    /* Channel 6 address extension reg */
        !           166: #define DMA_7XADR       0x8A    /* Channel 7 address extension reg */
        !           167: 
        !           168: 
        !           169: #define DMA_MSK         0x0A    /* Mask, enable disk, disable others */
        !           170: #define DMA_CLEAR       0x1A    /* Master clear */
        !           171: #define IOCR            0x56    /* IO controller */
        !           172: 
        !           173: /*
        !           174:  * DMA Channels. d_chan field of dmareq.
        !           175:  */
        !           176: 
        !           177: #define NCHANS          8
        !           178: 
        !           179: /* 8 bit channels */
        !           180: #define DMA_CH0         0       /* Channel 0 */
        !           181: #define DMA_CH1         1       /* Channel 1 */
        !           182: #define DMA_CH2         2       /* Channel 2 */
        !           183: #define DMA_CH3         3       /* Channel 3 */
        !           184: /* 16 bit channels */
        !           185: #define DMA_CH4         4       /* Channel 4 */
        !           186: #define DMA_CH5         5       /* Channel 5 */
        !           187: #define DMA_CH6         6       /* Channel 6 */
        !           188: #define DMA_CH7         7       /* Channel 7 */
        !           189: 
        !           190: /*
        !           191:  * DMA Masks.
        !           192:  */
        !           193: #define DMA_SETMSK      4       /* Set mask bit */
        !           194: #define DMA_CLRMSK      0       /* Clear mask bit */
        !           195: #define DMA_RD          1
        !           196: #define DMA_WR          2
        !           197: #define DMA_VR          0
        !           198: 
        !           199: /* from memory to device */
        !           200: #define DMA_Wrmode      0x48    /* single, read, increment, no auto-init */
        !           201: /* from device to memory */
        !           202: #define DMA_Rdmode      0x44    /* single, write, increment, no auto-init */
        !           203: #define DMA_Nomode      0x0C    /* illegal mode */
        !           204: 
        !           205: #define DMAPRI  PRIBIO
        !           206: 
        !           207: /* dma_alloc modes */
        !           208: #define DMA_BLOCK       0       /* blocking task time allocation */
        !           209: #define DMA_NBLOCK      1       /* non-blocking task time allocation */
        !           210: 
        !           211: #define EISA_DMA_8      0       /* 8-bit data path */
        !           212: #define EISA_DMA_16     1       /* 16-bit data path, word count */
        !           213: #define EISA_DMA_32     2       /* 32-bit data path */
        !           214: #define EISA_DMA_16B    3       /* 16-bit data path, byte count */
        !           215: 
        !           216: #define EISA_ENCM       4       /* enable chaining mode */
        !           217: #define EISA_CMOK       8       /* chaining mode completed (OK) */
        !           218: 
        !           219: 
        !           220: /*
        !           221: Channel Address Array - make's life much easier
        !           222: */
        !           223: struct d37A_chan_reg_addr {
        !           224:         unsigned char   addr_reg;       /* target address register */
        !           225:         unsigned char   cnt_reg;        /* count register */
        !           226:         unsigned char   page_reg;       /* page register */
        !           227:         unsigned char   ff_reg;         /* first-last flipflop */
        !           228:         unsigned char   cmd_reg;        /* command register */
        !           229:         unsigned char   mode_reg;       /* mode register */
        !           230:         unsigned char   mask_reg;       /* mask register */
        !           231:         unsigned char   stat_reg;       /* status register */
        !           232:         unsigned char   reqt_reg;       /* request register */
        !           233:         unsigned short  hpage_reg;      /* high page register */
        !           234:         unsigned short  hcnt_reg;       /* high count register */
        !           235:         unsigned short  xmode_reg;      /* extended mode register */
        !           236:         unsigned short  scm_reg;        /* set chaining mode register */
        !           237: };
        !           238: 
        !           239: /*
        !           240: macro to initialize array of d37A_chan_reg_addr structures
        !           241: */
        !           242: #define D37A_BASE_REGS_VALUES \
        !           243:         {DMA_0ADR, DMA_0WCNT, DMACH0PG, CTL1_CLFF, \
        !           244:         CTL1_CMD, CTL1_MODE, CTL1_MASK, CTL1_STAT, CTL1_REQ, \
        !           245:         DMACH0HPG, DMACH0CCH, CTL1_EWM, CTL1_SCM}, \
        !           246:         {DMA_1ADR, DMA_1WCNT, DMACH1PG,  CTL1_CLFF, \
        !           247:         CTL1_CMD, CTL1_MODE, CTL1_MASK, CTL1_STAT, CTL1_REQ, \
        !           248:         DMACH1HPG, DMACH1CCH, CTL1_EWM, CTL1_SCM}, \
        !           249:         {DMA_2ADR, DMA_2WCNT, DMACH2PG,  CTL1_CLFF, \
        !           250:         CTL1_CMD, CTL1_MODE, CTL1_MASK, CTL1_STAT, CTL1_REQ, \
        !           251:         DMACH2HPG, DMACH2CCH, CTL1_EWM, CTL1_SCM}, \
        !           252:         {DMA_3ADR, DMA_3WCNT, DMACH3PG,  CTL1_CLFF, \
        !           253:         CTL1_CMD, CTL1_MODE, CTL1_MASK, CTL1_STAT, CTL1_REQ, \
        !           254:         DMACH3HPG, DMACH3CCH, CTL1_EWM, CTL1_SCM}, \
        !           255:         {DMA_4ADR, DMA_4WCNT, DMACH4PG,  CTL2_CLFF, \
        !           256:         CTL2_CMD, CTL2_MODE, CTL2_MASK, CTL2_STAT, CTL2_REQ, \
        !           257:         DMACH4HPG, DMACH4CCH, CTL2_EWM, CTL2_SCM}, \
        !           258:         {DMA_5ADR, DMA_5WCNT, DMACH5PG,  CTL2_CLFF, \
        !           259:         CTL2_CMD, CTL2_MODE, CTL2_MASK, CTL2_STAT, CTL2_REQ, \
        !           260:         DMACH5HPG, DMACH5CCH, CTL2_EWM, CTL2_SCM}, \
        !           261:         {DMA_6ADR, DMA_6WCNT, DMACH6PG,  CTL2_CLFF, \
        !           262:         CTL2_CMD, CTL2_MODE, CTL2_MASK, CTL2_STAT, CTL2_REQ, \
        !           263:         DMACH6HPG, DMACH6CCH, CTL2_EWM, CTL2_SCM}, \
        !           264:         {DMA_7ADR, DMA_7WCNT, DMACH7PG,  CTL2_CLFF, \
        !           265:         CTL2_CMD, CTL2_MODE, CTL2_MASK, CTL2_STAT, CTL2_REQ, \
        !           266:         DMACH7HPG, DMACH7CCH, CTL2_EWM, CTL2_SCM}
        !           267: 
        !           268: #endif

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